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Issue 169533002: A64: Tidy up Push and Pop TODOs. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Rebase after Abort code-size optimizations. Created 6 years, 10 months ago
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1 // Copyright 2013 the V8 project authors. All rights reserved. 1 // Copyright 2013 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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8432 } 8432 }
8433 } 8433 }
8434 8434
8435 8435
8436 // Push and pop data using overlapping X- and W-sized quantities. 8436 // Push and pop data using overlapping X- and W-sized quantities.
8437 static void PushPopJsspWXOverlapHelper(int reg_count, int claim) { 8437 static void PushPopJsspWXOverlapHelper(int reg_count, int claim) {
8438 // This test emits rather a lot of code. 8438 // This test emits rather a lot of code.
8439 SETUP_SIZE(BUF_SIZE * 2); 8439 SETUP_SIZE(BUF_SIZE * 2);
8440 8440
8441 // Work out which registers to use, based on reg_size. 8441 // Work out which registers to use, based on reg_size.
8442 static RegList const allowed = ~(x8.Bit() | x9.Bit() | jssp.Bit()); 8442 Register tmp = x8;
8443 static RegList const allowed = ~(tmp.Bit() | jssp.Bit());
8443 if (reg_count == kPushPopJsspMaxRegCount) { 8444 if (reg_count == kPushPopJsspMaxRegCount) {
8444 reg_count = CountSetBits(allowed, kNumberOfRegisters); 8445 reg_count = CountSetBits(allowed, kNumberOfRegisters);
8445 } 8446 }
8446 Register w[kNumberOfRegisters]; 8447 Register w[kNumberOfRegisters];
8447 Register x[kNumberOfRegisters]; 8448 Register x[kNumberOfRegisters];
8448 RegList list = PopulateRegisterArray(w, x, NULL, 0, reg_count, allowed); 8449 RegList list = PopulateRegisterArray(w, x, NULL, 0, reg_count, allowed);
8449 8450
8450 // The number of W-sized slots we expect to pop. When we pop, we alternate 8451 // The number of W-sized slots we expect to pop. When we pop, we alternate
8451 // between W and X registers, so we need reg_count*1.5 W-sized slots. 8452 // between W and X registers, so we need reg_count*1.5 W-sized slots.
8452 int const requested_w_slots = reg_count + reg_count / 2; 8453 int const requested_w_slots = reg_count + reg_count / 2;
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8518 8519
8519 int active_w_slots = 0; 8520 int active_w_slots = 0;
8520 for (int i = 0; active_w_slots < requested_w_slots; i++) { 8521 for (int i = 0; active_w_slots < requested_w_slots; i++) {
8521 ASSERT(i < reg_count); 8522 ASSERT(i < reg_count);
8522 // In order to test various arguments to PushMultipleTimes, and to try to 8523 // In order to test various arguments to PushMultipleTimes, and to try to
8523 // exercise different alignment and overlap effects, we push each 8524 // exercise different alignment and overlap effects, we push each
8524 // register a different number of times. 8525 // register a different number of times.
8525 int times = i % 4 + 1; 8526 int times = i % 4 + 1;
8526 if (i & 1) { 8527 if (i & 1) {
8527 // Push odd-numbered registers as W registers. 8528 // Push odd-numbered registers as W registers.
8528 __ PushMultipleTimes(times, w[i]); 8529 if (i & 2) {
8530 __ PushMultipleTimes(w[i], times);
8531 } else {
8532 // Use a register to specify the count.
8533 __ Mov(tmp.W(), times);
8534 __ PushMultipleTimes(w[i], tmp.W());
8535 }
8529 // Fill in the expected stack slots. 8536 // Fill in the expected stack slots.
8530 for (int j = 0; j < times; j++) { 8537 for (int j = 0; j < times; j++) {
8531 if (w[i].Is(wzr)) { 8538 if (w[i].Is(wzr)) {
8532 // The zero register always writes zeroes. 8539 // The zero register always writes zeroes.
8533 stack[active_w_slots++] = 0; 8540 stack[active_w_slots++] = 0;
8534 } else { 8541 } else {
8535 stack[active_w_slots++] = literal_base_w * i; 8542 stack[active_w_slots++] = literal_base_w * i;
8536 } 8543 }
8537 } 8544 }
8538 } else { 8545 } else {
8539 // Push even-numbered registers as X registers. 8546 // Push even-numbered registers as X registers.
8540 __ PushMultipleTimes(times, x[i]); 8547 if (i & 2) {
8548 __ PushMultipleTimes(x[i], times);
8549 } else {
8550 // Use a register to specify the count.
8551 __ Mov(tmp, times);
8552 __ PushMultipleTimes(x[i], tmp);
8553 }
8541 // Fill in the expected stack slots. 8554 // Fill in the expected stack slots.
8542 for (int j = 0; j < times; j++) { 8555 for (int j = 0; j < times; j++) {
8543 if (x[i].IsZero()) { 8556 if (x[i].IsZero()) {
8544 // The zero register always writes zeroes. 8557 // The zero register always writes zeroes.
8545 stack[active_w_slots++] = 0; 8558 stack[active_w_slots++] = 0;
8546 stack[active_w_slots++] = 0; 8559 stack[active_w_slots++] = 0;
8547 } else { 8560 } else {
8548 stack[active_w_slots++] = literal_base_hi * i; 8561 stack[active_w_slots++] = literal_base_hi * i;
8549 stack[active_w_slots++] = literal_base_lo * i; 8562 stack[active_w_slots++] = literal_base_lo * i;
8550 } 8563 }
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8721 ASSERT_EQUAL_64(0x3333333333333333UL, x26); 8734 ASSERT_EQUAL_64(0x3333333333333333UL, x26);
8722 8735
8723 ASSERT_EQUAL_32(0x33333333U, w25); 8736 ASSERT_EQUAL_32(0x33333333U, w25);
8724 ASSERT_EQUAL_32(0x00000000U, w27); 8737 ASSERT_EQUAL_32(0x00000000U, w27);
8725 ASSERT_EQUAL_32(0x22222222U, w28); 8738 ASSERT_EQUAL_32(0x22222222U, w28);
8726 ASSERT_EQUAL_32(0x33333333U, w29); 8739 ASSERT_EQUAL_32(0x33333333U, w29);
8727 TEARDOWN(); 8740 TEARDOWN();
8728 } 8741 }
8729 8742
8730 8743
8744 TEST(push_queued) {
8745 INIT_V8();
8746 SETUP();
8747
8748 START();
8749
8750 ASSERT(__ StackPointer().Is(csp));
8751 __ Mov(jssp, __ StackPointer());
8752 __ SetStackPointer(jssp);
8753
8754 MacroAssembler::PushPopQueue queue(&masm);
8755
8756 // Queue up registers.
8757 queue.Queue(x0);
8758 queue.Queue(x1);
8759 queue.Queue(x2);
8760 queue.Queue(x3);
8761
8762 queue.Queue(w4);
8763 queue.Queue(w5);
8764 queue.Queue(w6);
8765
8766 queue.Queue(d0);
8767 queue.Queue(d1);
8768
8769 queue.Queue(s2);
8770
8771 __ Mov(x0, 0x1234000000000000);
8772 __ Mov(x1, 0x1234000100010001);
8773 __ Mov(x2, 0x1234000200020002);
8774 __ Mov(x3, 0x1234000300030003);
8775 __ Mov(w4, 0x12340004);
8776 __ Mov(w5, 0x12340005);
8777 __ Mov(w6, 0x12340006);
8778 __ Fmov(d0, 123400.0);
8779 __ Fmov(d1, 123401.0);
8780 __ Fmov(s2, 123402.0);
8781
8782 // Actually push them.
8783 queue.PushQueued();
8784
8785 Clobber(&masm, CPURegList(CPURegister::kRegister, kXRegSize, 0, 6));
8786 Clobber(&masm, CPURegList(CPURegister::kFPRegister, kDRegSize, 0, 2));
8787
8788 // Pop them conventionally.
8789 __ Pop(s2);
8790 __ Pop(d1, d0);
8791 __ Pop(w6, w5, w4);
8792 __ Pop(x3, x2, x1, x0);
8793
8794 __ Mov(csp, __ StackPointer());
8795 __ SetStackPointer(csp);
8796
8797 END();
8798
8799 RUN();
8800
8801 ASSERT_EQUAL_64(0x1234000000000000, x0);
8802 ASSERT_EQUAL_64(0x1234000100010001, x1);
8803 ASSERT_EQUAL_64(0x1234000200020002, x2);
8804 ASSERT_EQUAL_64(0x1234000300030003, x3);
8805
8806 ASSERT_EQUAL_32(0x12340004, w4);
8807 ASSERT_EQUAL_32(0x12340005, w5);
8808 ASSERT_EQUAL_32(0x12340006, w6);
8809
8810 ASSERT_EQUAL_FP64(123400.0, d0);
8811 ASSERT_EQUAL_FP64(123401.0, d1);
8812
8813 ASSERT_EQUAL_FP32(123402.0, s2);
8814
8815 TEARDOWN();
8816 }
8817
8818
8819 TEST(pop_queued) {
8820 INIT_V8();
8821 SETUP();
8822
8823 START();
8824
8825 ASSERT(__ StackPointer().Is(csp));
8826 __ Mov(jssp, __ StackPointer());
8827 __ SetStackPointer(jssp);
8828
8829 MacroAssembler::PushPopQueue queue(&masm);
8830
8831 __ Mov(x0, 0x1234000000000000);
8832 __ Mov(x1, 0x1234000100010001);
8833 __ Mov(x2, 0x1234000200020002);
8834 __ Mov(x3, 0x1234000300030003);
8835 __ Mov(w4, 0x12340004);
8836 __ Mov(w5, 0x12340005);
8837 __ Mov(w6, 0x12340006);
8838 __ Fmov(d0, 123400.0);
8839 __ Fmov(d1, 123401.0);
8840 __ Fmov(s2, 123402.0);
8841
8842 // Push registers conventionally.
8843 __ Push(x0, x1, x2, x3);
8844 __ Push(w4, w5, w6);
8845 __ Push(d0, d1);
8846 __ Push(s2);
8847
8848 // Queue up a pop.
8849 queue.Queue(s2);
8850
8851 queue.Queue(d1);
8852 queue.Queue(d0);
8853
8854 queue.Queue(w6);
8855 queue.Queue(w5);
8856 queue.Queue(w4);
8857
8858 queue.Queue(x3);
8859 queue.Queue(x2);
8860 queue.Queue(x1);
8861 queue.Queue(x0);
8862
8863 Clobber(&masm, CPURegList(CPURegister::kRegister, kXRegSize, 0, 6));
8864 Clobber(&masm, CPURegList(CPURegister::kFPRegister, kDRegSize, 0, 2));
8865
8866 // Actually pop them.
8867 queue.PopQueued();
8868
8869 __ Mov(csp, __ StackPointer());
8870 __ SetStackPointer(csp);
8871
8872 END();
8873
8874 RUN();
8875
8876 ASSERT_EQUAL_64(0x1234000000000000, x0);
8877 ASSERT_EQUAL_64(0x1234000100010001, x1);
8878 ASSERT_EQUAL_64(0x1234000200020002, x2);
8879 ASSERT_EQUAL_64(0x1234000300030003, x3);
8880
8881 ASSERT_EQUAL_64(0x0000000012340004, x4);
8882 ASSERT_EQUAL_64(0x0000000012340005, x5);
8883 ASSERT_EQUAL_64(0x0000000012340006, x6);
8884
8885 ASSERT_EQUAL_FP64(123400.0, d0);
8886 ASSERT_EQUAL_FP64(123401.0, d1);
8887
8888 ASSERT_EQUAL_FP32(123402.0, s2);
8889
8890 TEARDOWN();
8891 }
8892
8893
8731 TEST(jump_both_smi) { 8894 TEST(jump_both_smi) {
8732 INIT_V8(); 8895 INIT_V8();
8733 SETUP(); 8896 SETUP();
8734 8897
8735 Label cond_pass_00, cond_pass_01, cond_pass_10, cond_pass_11; 8898 Label cond_pass_00, cond_pass_01, cond_pass_10, cond_pass_11;
8736 Label cond_fail_00, cond_fail_01, cond_fail_10, cond_fail_11; 8899 Label cond_fail_00, cond_fail_01, cond_fail_10, cond_fail_11;
8737 Label return1, return2, return3, done; 8900 Label return1, return2, return3, done;
8738 8901
8739 START(); 8902 START();
8740 8903
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9794 AbsHelperX(-42); 9957 AbsHelperX(-42);
9795 AbsHelperX(kXMinInt); 9958 AbsHelperX(kXMinInt);
9796 AbsHelperX(kXMaxInt); 9959 AbsHelperX(kXMaxInt);
9797 9960
9798 AbsHelperW(0); 9961 AbsHelperW(0);
9799 AbsHelperW(42); 9962 AbsHelperW(42);
9800 AbsHelperW(-42); 9963 AbsHelperW(-42);
9801 AbsHelperW(kWMinInt); 9964 AbsHelperW(kWMinInt);
9802 AbsHelperW(kWMaxInt); 9965 AbsHelperW(kWMaxInt);
9803 } 9966 }
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