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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions are | 5 // modification, are permitted provided that the following conditions are |
6 // met: | 6 // met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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297 reg_code = f; | 297 reg_code = f; |
298 DCHECK(is_valid()); | 298 DCHECK(is_valid()); |
299 } | 299 } |
300 // Unfortunately we can't make this private in a struct. | 300 // Unfortunately we can't make this private in a struct. |
301 int reg_code; | 301 int reg_code; |
302 }; | 302 }; |
303 | 303 |
304 const FPUControlRegister no_fpucreg = { kInvalidFPUControlRegister }; | 304 const FPUControlRegister no_fpucreg = { kInvalidFPUControlRegister }; |
305 const FPUControlRegister FCSR = { kFCSRRegister }; | 305 const FPUControlRegister FCSR = { kFCSRRegister }; |
306 | 306 |
| 307 // TODO(mips) Define SIMD registers. |
| 308 typedef DoubleRegister Simd128Register; |
307 | 309 |
308 // ----------------------------------------------------------------------------- | 310 // ----------------------------------------------------------------------------- |
309 // Machine instruction Operands. | 311 // Machine instruction Operands. |
310 | 312 |
311 // Class Operand represents a shifter operand in data processing instructions. | 313 // Class Operand represents a shifter operand in data processing instructions. |
312 class Operand BASE_EMBEDDED { | 314 class Operand BASE_EMBEDDED { |
313 public: | 315 public: |
314 // Immediate. | 316 // Immediate. |
315 INLINE(explicit Operand(int32_t immediate, | 317 INLINE(explicit Operand(int32_t immediate, |
316 RelocInfo::Mode rmode = RelocInfo::NONE32)); | 318 RelocInfo::Mode rmode = RelocInfo::NONE32)); |
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1438 public: | 1440 public: |
1439 explicit EnsureSpace(Assembler* assembler) { | 1441 explicit EnsureSpace(Assembler* assembler) { |
1440 assembler->CheckBuffer(); | 1442 assembler->CheckBuffer(); |
1441 } | 1443 } |
1442 }; | 1444 }; |
1443 | 1445 |
1444 } // namespace internal | 1446 } // namespace internal |
1445 } // namespace v8 | 1447 } // namespace v8 |
1446 | 1448 |
1447 #endif // V8_ARM_ASSEMBLER_MIPS_H_ | 1449 #endif // V8_ARM_ASSEMBLER_MIPS_H_ |
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