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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #ifndef V8_COMPILER_INSTRUCTION_H_ | 5 #ifndef V8_COMPILER_INSTRUCTION_H_ |
6 #define V8_COMPILER_INSTRUCTION_H_ | 6 #define V8_COMPILER_INSTRUCTION_H_ |
7 | 7 |
8 #include <deque> | 8 #include <deque> |
9 #include <iosfwd> | 9 #include <iosfwd> |
10 #include <map> | 10 #include <map> |
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60 // associated with a virtual register | 60 // associated with a virtual register |
61 INSTRUCTION_OPERAND_PREDICATE(Explicit, EXPLICIT) | 61 INSTRUCTION_OPERAND_PREDICATE(Explicit, EXPLICIT) |
62 // AllocatedOperands are registers or stack slots that are assigned by the | 62 // AllocatedOperands are registers or stack slots that are assigned by the |
63 // register allocator and are always associated with a virtual register. | 63 // register allocator and are always associated with a virtual register. |
64 INSTRUCTION_OPERAND_PREDICATE(Allocated, ALLOCATED) | 64 INSTRUCTION_OPERAND_PREDICATE(Allocated, ALLOCATED) |
65 #undef INSTRUCTION_OPERAND_PREDICATE | 65 #undef INSTRUCTION_OPERAND_PREDICATE |
66 | 66 |
67 inline bool IsAnyRegister() const; | 67 inline bool IsAnyRegister() const; |
68 inline bool IsRegister() const; | 68 inline bool IsRegister() const; |
69 inline bool IsDoubleRegister() const; | 69 inline bool IsDoubleRegister() const; |
| 70 inline bool IsSimd128Register() const; |
70 inline bool IsStackSlot() const; | 71 inline bool IsStackSlot() const; |
71 inline bool IsDoubleStackSlot() const; | 72 inline bool IsDoubleStackSlot() const; |
| 73 inline bool IsSimd128StackSlot() const; |
72 | 74 |
73 template <typename SubKindOperand> | 75 template <typename SubKindOperand> |
74 static SubKindOperand* New(Zone* zone, const SubKindOperand& op) { | 76 static SubKindOperand* New(Zone* zone, const SubKindOperand& op) { |
75 void* buffer = zone->New(sizeof(op)); | 77 void* buffer = zone->New(sizeof(op)); |
76 return new (buffer) SubKindOperand(op); | 78 return new (buffer) SubKindOperand(op); |
77 } | 79 } |
78 | 80 |
79 static void ReplaceWith(InstructionOperand* dest, | 81 static void ReplaceWith(InstructionOperand* dest, |
80 const InstructionOperand* src) { | 82 const InstructionOperand* src) { |
81 *dest = *src; | 83 *dest = *src; |
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404 MachineRepresentation rep, int index) | 406 MachineRepresentation rep, int index) |
405 : InstructionOperand(operand_kind) { | 407 : InstructionOperand(operand_kind) { |
406 DCHECK_IMPLIES(location_kind == REGISTER, index >= 0); | 408 DCHECK_IMPLIES(location_kind == REGISTER, index >= 0); |
407 DCHECK(IsSupportedRepresentation(rep)); | 409 DCHECK(IsSupportedRepresentation(rep)); |
408 value_ |= LocationKindField::encode(location_kind); | 410 value_ |= LocationKindField::encode(location_kind); |
409 value_ |= RepresentationField::encode(rep); | 411 value_ |= RepresentationField::encode(rep); |
410 value_ |= static_cast<int64_t>(index) << IndexField::kShift; | 412 value_ |= static_cast<int64_t>(index) << IndexField::kShift; |
411 } | 413 } |
412 | 414 |
413 int index() const { | 415 int index() const { |
414 DCHECK(IsStackSlot() || IsDoubleStackSlot()); | 416 DCHECK(IsStackSlot() || IsDoubleStackSlot() || IsSimd128StackSlot()); |
415 return static_cast<int64_t>(value_) >> IndexField::kShift; | 417 return static_cast<int64_t>(value_) >> IndexField::kShift; |
416 } | 418 } |
417 | 419 |
418 Register GetRegister() const { | 420 Register GetRegister() const { |
419 DCHECK(IsRegister()); | 421 DCHECK(IsRegister()); |
420 return Register::from_code(static_cast<int64_t>(value_) >> | 422 return Register::from_code(static_cast<int64_t>(value_) >> |
421 IndexField::kShift); | 423 IndexField::kShift); |
422 } | 424 } |
423 | 425 |
424 DoubleRegister GetDoubleRegister() const { | 426 DoubleRegister GetDoubleRegister() const { |
425 DCHECK(IsDoubleRegister()); | 427 DCHECK(IsDoubleRegister()); |
426 return DoubleRegister::from_code(static_cast<int64_t>(value_) >> | 428 return DoubleRegister::from_code(static_cast<int64_t>(value_) >> |
427 IndexField::kShift); | 429 IndexField::kShift); |
428 } | 430 } |
429 | 431 |
| 432 Simd128Register GetSimd128Register() const { |
| 433 DCHECK(IsSimd128Register()); |
| 434 return Simd128Register::from_code(static_cast<int64_t>(value_) >> |
| 435 IndexField::kShift); |
| 436 } |
| 437 |
430 LocationKind location_kind() const { | 438 LocationKind location_kind() const { |
431 return LocationKindField::decode(value_); | 439 return LocationKindField::decode(value_); |
432 } | 440 } |
433 | 441 |
434 MachineRepresentation representation() const { | 442 MachineRepresentation representation() const { |
435 return RepresentationField::decode(value_); | 443 return RepresentationField::decode(value_); |
436 } | 444 } |
437 | 445 |
438 static bool IsSupportedRepresentation(MachineRepresentation rep) { | 446 static bool IsSupportedRepresentation(MachineRepresentation rep) { |
439 switch (rep) { | 447 switch (rep) { |
440 case MachineRepresentation::kWord32: | 448 case MachineRepresentation::kWord32: |
441 case MachineRepresentation::kWord64: | 449 case MachineRepresentation::kWord64: |
442 case MachineRepresentation::kFloat32: | 450 case MachineRepresentation::kFloat32: |
443 case MachineRepresentation::kFloat64: | 451 case MachineRepresentation::kFloat64: |
| 452 case MachineRepresentation::kSimd128: |
444 case MachineRepresentation::kTagged: | 453 case MachineRepresentation::kTagged: |
445 return true; | 454 return true; |
446 case MachineRepresentation::kBit: | 455 case MachineRepresentation::kBit: |
447 case MachineRepresentation::kWord8: | 456 case MachineRepresentation::kWord8: |
448 case MachineRepresentation::kWord16: | 457 case MachineRepresentation::kWord16: |
449 case MachineRepresentation::kNone: | 458 case MachineRepresentation::kNone: |
450 return false; | 459 return false; |
451 } | 460 } |
452 UNREACHABLE(); | 461 UNREACHABLE(); |
453 return false; | 462 return false; |
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515 bool InstructionOperand::IsRegister() const { | 524 bool InstructionOperand::IsRegister() const { |
516 return IsAnyRegister() && | 525 return IsAnyRegister() && |
517 !IsFloatingPoint(LocationOperand::cast(this)->representation()); | 526 !IsFloatingPoint(LocationOperand::cast(this)->representation()); |
518 } | 527 } |
519 | 528 |
520 bool InstructionOperand::IsDoubleRegister() const { | 529 bool InstructionOperand::IsDoubleRegister() const { |
521 return IsAnyRegister() && | 530 return IsAnyRegister() && |
522 IsFloatingPoint(LocationOperand::cast(this)->representation()); | 531 IsFloatingPoint(LocationOperand::cast(this)->representation()); |
523 } | 532 } |
524 | 533 |
| 534 bool InstructionOperand::IsSimd128Register() const { |
| 535 return IsAnyRegister() && |
| 536 LocationOperand::cast(this)->representation() == |
| 537 MachineRepresentation::kSimd128; |
| 538 } |
| 539 |
525 bool InstructionOperand::IsStackSlot() const { | 540 bool InstructionOperand::IsStackSlot() const { |
526 return (IsAllocated() || IsExplicit()) && | 541 return (IsAllocated() || IsExplicit()) && |
527 LocationOperand::cast(this)->location_kind() == | 542 LocationOperand::cast(this)->location_kind() == |
528 LocationOperand::STACK_SLOT && | 543 LocationOperand::STACK_SLOT && |
529 !IsFloatingPoint(LocationOperand::cast(this)->representation()); | 544 !IsFloatingPoint(LocationOperand::cast(this)->representation()); |
530 } | 545 } |
531 | 546 |
532 bool InstructionOperand::IsDoubleStackSlot() const { | 547 bool InstructionOperand::IsDoubleStackSlot() const { |
533 return (IsAllocated() || IsExplicit()) && | 548 return (IsAllocated() || IsExplicit()) && |
534 LocationOperand::cast(this)->location_kind() == | 549 LocationOperand::cast(this)->location_kind() == |
535 LocationOperand::STACK_SLOT && | 550 LocationOperand::STACK_SLOT && |
536 IsFloatingPoint(LocationOperand::cast(this)->representation()); | 551 IsFloatingPoint(LocationOperand::cast(this)->representation()); |
537 } | 552 } |
538 | 553 |
| 554 bool InstructionOperand::IsSimd128StackSlot() const { |
| 555 return (IsAllocated() || IsExplicit()) && |
| 556 LocationOperand::cast(this)->location_kind() == |
| 557 LocationOperand::STACK_SLOT && |
| 558 LocationOperand::cast(this)->representation() == |
| 559 MachineRepresentation::kSimd128; |
| 560 } |
| 561 |
539 uint64_t InstructionOperand::GetCanonicalizedValue() const { | 562 uint64_t InstructionOperand::GetCanonicalizedValue() const { |
540 if (IsAllocated() || IsExplicit()) { | 563 if (IsAllocated() || IsExplicit()) { |
541 // TODO(dcarney): put machine type last and mask. | 564 // TODO(dcarney): put machine type last and mask. |
542 MachineRepresentation canonicalized_representation = | 565 MachineRepresentation canonicalized_representation = |
543 IsFloatingPoint(LocationOperand::cast(this)->representation()) | 566 IsFloatingPoint(LocationOperand::cast(this)->representation()) |
544 ? MachineRepresentation::kFloat64 | 567 ? MachineRepresentation::kFloat64 |
545 : MachineRepresentation::kNone; | 568 : MachineRepresentation::kNone; |
546 return InstructionOperand::KindField::update( | 569 return InstructionOperand::KindField::update( |
547 LocationOperand::RepresentationField::update( | 570 LocationOperand::RepresentationField::update( |
548 this->value_, canonicalized_representation), | 571 this->value_, canonicalized_representation), |
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1364 | 1387 |
1365 | 1388 |
1366 std::ostream& operator<<(std::ostream& os, | 1389 std::ostream& operator<<(std::ostream& os, |
1367 const PrintableInstructionSequence& code); | 1390 const PrintableInstructionSequence& code); |
1368 | 1391 |
1369 } // namespace compiler | 1392 } // namespace compiler |
1370 } // namespace internal | 1393 } // namespace internal |
1371 } // namespace v8 | 1394 } // namespace v8 |
1372 | 1395 |
1373 #endif // V8_COMPILER_INSTRUCTION_H_ | 1396 #endif // V8_COMPILER_INSTRUCTION_H_ |
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