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| 1 // Copyright 2013 the V8 project authors. All rights reserved. | 1 // Copyright 2013 the V8 project authors. All rights reserved. |
| 2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
| 3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
| 4 // met: | 4 // met: |
| 5 // | 5 // |
| 6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
| 7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
| 8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
| 9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
| 10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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| 8103 } | 8103 } |
| 8104 } | 8104 } |
| 8105 | 8105 |
| 8106 | 8106 |
| 8107 // Push and pop data using overlapping X- and W-sized quantities. | 8107 // Push and pop data using overlapping X- and W-sized quantities. |
| 8108 static void PushPopJsspWXOverlapHelper(int reg_count, int claim) { | 8108 static void PushPopJsspWXOverlapHelper(int reg_count, int claim) { |
| 8109 // This test emits rather a lot of code. | 8109 // This test emits rather a lot of code. |
| 8110 SETUP_SIZE(BUF_SIZE * 2); | 8110 SETUP_SIZE(BUF_SIZE * 2); |
| 8111 | 8111 |
| 8112 // Work out which registers to use, based on reg_size. | 8112 // Work out which registers to use, based on reg_size. |
| 8113 Register tmp = x8; | 8113 static RegList const allowed = ~(x8.Bit() | x9.Bit() | jssp.Bit()); |
| 8114 static RegList const allowed = ~(tmp.Bit() | jssp.Bit()); | |
| 8115 if (reg_count == kPushPopJsspMaxRegCount) { | 8114 if (reg_count == kPushPopJsspMaxRegCount) { |
| 8116 reg_count = CountSetBits(allowed, kNumberOfRegisters); | 8115 reg_count = CountSetBits(allowed, kNumberOfRegisters); |
| 8117 } | 8116 } |
| 8118 Register w[kNumberOfRegisters]; | 8117 Register w[kNumberOfRegisters]; |
| 8119 Register x[kNumberOfRegisters]; | 8118 Register x[kNumberOfRegisters]; |
| 8120 RegList list = PopulateRegisterArray(w, x, NULL, 0, reg_count, allowed); | 8119 RegList list = PopulateRegisterArray(w, x, NULL, 0, reg_count, allowed); |
| 8121 | 8120 |
| 8122 // The number of W-sized slots we expect to pop. When we pop, we alternate | 8121 // The number of W-sized slots we expect to pop. When we pop, we alternate |
| 8123 // between W and X registers, so we need reg_count*1.5 W-sized slots. | 8122 // between W and X registers, so we need reg_count*1.5 W-sized slots. |
| 8124 int const requested_w_slots = reg_count + reg_count / 2; | 8123 int const requested_w_slots = reg_count + reg_count / 2; |
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| 8190 | 8189 |
| 8191 int active_w_slots = 0; | 8190 int active_w_slots = 0; |
| 8192 for (int i = 0; active_w_slots < requested_w_slots; i++) { | 8191 for (int i = 0; active_w_slots < requested_w_slots; i++) { |
| 8193 ASSERT(i < reg_count); | 8192 ASSERT(i < reg_count); |
| 8194 // In order to test various arguments to PushMultipleTimes, and to try to | 8193 // In order to test various arguments to PushMultipleTimes, and to try to |
| 8195 // exercise different alignment and overlap effects, we push each | 8194 // exercise different alignment and overlap effects, we push each |
| 8196 // register a different number of times. | 8195 // register a different number of times. |
| 8197 int times = i % 4 + 1; | 8196 int times = i % 4 + 1; |
| 8198 if (i & 1) { | 8197 if (i & 1) { |
| 8199 // Push odd-numbered registers as W registers. | 8198 // Push odd-numbered registers as W registers. |
| 8200 if (i & 2) { | 8199 __ PushMultipleTimes(times, w[i]); |
| 8201 __ PushMultipleTimes(w[i], times); | |
| 8202 } else { | |
| 8203 // Use a register to specify the count. | |
| 8204 __ Mov(tmp.W(), times); | |
| 8205 __ PushMultipleTimes(w[i], tmp.W()); | |
| 8206 } | |
| 8207 // Fill in the expected stack slots. | 8200 // Fill in the expected stack slots. |
| 8208 for (int j = 0; j < times; j++) { | 8201 for (int j = 0; j < times; j++) { |
| 8209 if (w[i].Is(wzr)) { | 8202 if (w[i].Is(wzr)) { |
| 8210 // The zero register always writes zeroes. | 8203 // The zero register always writes zeroes. |
| 8211 stack[active_w_slots++] = 0; | 8204 stack[active_w_slots++] = 0; |
| 8212 } else { | 8205 } else { |
| 8213 stack[active_w_slots++] = literal_base_w * i; | 8206 stack[active_w_slots++] = literal_base_w * i; |
| 8214 } | 8207 } |
| 8215 } | 8208 } |
| 8216 } else { | 8209 } else { |
| 8217 // Push even-numbered registers as X registers. | 8210 // Push even-numbered registers as X registers. |
| 8218 if (i & 2) { | 8211 __ PushMultipleTimes(times, x[i]); |
| 8219 __ PushMultipleTimes(x[i], times); | |
| 8220 } else { | |
| 8221 // Use a register to specify the count. | |
| 8222 __ Mov(tmp, times); | |
| 8223 __ PushMultipleTimes(x[i], tmp); | |
| 8224 } | |
| 8225 // Fill in the expected stack slots. | 8212 // Fill in the expected stack slots. |
| 8226 for (int j = 0; j < times; j++) { | 8213 for (int j = 0; j < times; j++) { |
| 8227 if (x[i].IsZero()) { | 8214 if (x[i].IsZero()) { |
| 8228 // The zero register always writes zeroes. | 8215 // The zero register always writes zeroes. |
| 8229 stack[active_w_slots++] = 0; | 8216 stack[active_w_slots++] = 0; |
| 8230 stack[active_w_slots++] = 0; | 8217 stack[active_w_slots++] = 0; |
| 8231 } else { | 8218 } else { |
| 8232 stack[active_w_slots++] = literal_base_hi * i; | 8219 stack[active_w_slots++] = literal_base_hi * i; |
| 8233 stack[active_w_slots++] = literal_base_lo * i; | 8220 stack[active_w_slots++] = literal_base_lo * i; |
| 8234 } | 8221 } |
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| 8405 ASSERT_EQUAL_64(0x3333333333333333UL, x26); | 8392 ASSERT_EQUAL_64(0x3333333333333333UL, x26); |
| 8406 | 8393 |
| 8407 ASSERT_EQUAL_32(0x33333333U, w25); | 8394 ASSERT_EQUAL_32(0x33333333U, w25); |
| 8408 ASSERT_EQUAL_32(0x00000000U, w27); | 8395 ASSERT_EQUAL_32(0x00000000U, w27); |
| 8409 ASSERT_EQUAL_32(0x22222222U, w28); | 8396 ASSERT_EQUAL_32(0x22222222U, w28); |
| 8410 ASSERT_EQUAL_32(0x33333333U, w29); | 8397 ASSERT_EQUAL_32(0x33333333U, w29); |
| 8411 TEARDOWN(); | 8398 TEARDOWN(); |
| 8412 } | 8399 } |
| 8413 | 8400 |
| 8414 | 8401 |
| 8415 TEST(push_queued) { | |
| 8416 INIT_V8(); | |
| 8417 SETUP(); | |
| 8418 | |
| 8419 START(); | |
| 8420 | |
| 8421 ASSERT(__ StackPointer().Is(csp)); | |
| 8422 __ Mov(jssp, __ StackPointer()); | |
| 8423 __ SetStackPointer(jssp); | |
| 8424 | |
| 8425 MacroAssembler::PushPopQueue queue(&masm); | |
| 8426 | |
| 8427 // Queue up registers. | |
| 8428 queue.Queue(x0); | |
| 8429 queue.Queue(x1); | |
| 8430 queue.Queue(x2); | |
| 8431 queue.Queue(x3); | |
| 8432 | |
| 8433 queue.Queue(w4); | |
| 8434 queue.Queue(w5); | |
| 8435 queue.Queue(w6); | |
| 8436 | |
| 8437 queue.Queue(d0); | |
| 8438 queue.Queue(d1); | |
| 8439 | |
| 8440 queue.Queue(s2); | |
| 8441 | |
| 8442 __ Mov(x0, 0x1234000000000000); | |
| 8443 __ Mov(x1, 0x1234000100010001); | |
| 8444 __ Mov(x2, 0x1234000200020002); | |
| 8445 __ Mov(x3, 0x1234000300030003); | |
| 8446 __ Mov(w4, 0x12340004); | |
| 8447 __ Mov(w5, 0x12340005); | |
| 8448 __ Mov(w6, 0x12340006); | |
| 8449 __ Fmov(d0, 123400.0); | |
| 8450 __ Fmov(d1, 123401.0); | |
| 8451 __ Fmov(s2, 123402.0); | |
| 8452 | |
| 8453 // Actually push them. | |
| 8454 queue.PushQueued(); | |
| 8455 | |
| 8456 Clobber(&masm, CPURegList(CPURegister::kRegister, kXRegSize, 0, 6)); | |
| 8457 Clobber(&masm, CPURegList(CPURegister::kFPRegister, kDRegSize, 0, 2)); | |
| 8458 | |
| 8459 // Pop them conventionally. | |
| 8460 __ Pop(s2); | |
| 8461 __ Pop(d1, d0); | |
| 8462 __ Pop(w6, w5, w4); | |
| 8463 __ Pop(x3, x2, x1, x0); | |
| 8464 | |
| 8465 __ Mov(csp, __ StackPointer()); | |
| 8466 __ SetStackPointer(csp); | |
| 8467 | |
| 8468 END(); | |
| 8469 | |
| 8470 RUN(); | |
| 8471 | |
| 8472 ASSERT_EQUAL_64(0x1234000000000000, x0); | |
| 8473 ASSERT_EQUAL_64(0x1234000100010001, x1); | |
| 8474 ASSERT_EQUAL_64(0x1234000200020002, x2); | |
| 8475 ASSERT_EQUAL_64(0x1234000300030003, x3); | |
| 8476 | |
| 8477 ASSERT_EQUAL_32(0x12340004, w4); | |
| 8478 ASSERT_EQUAL_32(0x12340005, w5); | |
| 8479 ASSERT_EQUAL_32(0x12340006, w6); | |
| 8480 | |
| 8481 ASSERT_EQUAL_FP64(123400.0, d0); | |
| 8482 ASSERT_EQUAL_FP64(123401.0, d1); | |
| 8483 | |
| 8484 ASSERT_EQUAL_FP32(123402.0, s2); | |
| 8485 | |
| 8486 TEARDOWN(); | |
| 8487 } | |
| 8488 | |
| 8489 | |
| 8490 TEST(pop_queued) { | |
| 8491 INIT_V8(); | |
| 8492 SETUP(); | |
| 8493 | |
| 8494 START(); | |
| 8495 | |
| 8496 ASSERT(__ StackPointer().Is(csp)); | |
| 8497 __ Mov(jssp, __ StackPointer()); | |
| 8498 __ SetStackPointer(jssp); | |
| 8499 | |
| 8500 MacroAssembler::PushPopQueue queue(&masm); | |
| 8501 | |
| 8502 __ Mov(x0, 0x1234000000000000); | |
| 8503 __ Mov(x1, 0x1234000100010001); | |
| 8504 __ Mov(x2, 0x1234000200020002); | |
| 8505 __ Mov(x3, 0x1234000300030003); | |
| 8506 __ Mov(w4, 0x12340004); | |
| 8507 __ Mov(w5, 0x12340005); | |
| 8508 __ Mov(w6, 0x12340006); | |
| 8509 __ Fmov(d0, 123400.0); | |
| 8510 __ Fmov(d1, 123401.0); | |
| 8511 __ Fmov(s2, 123402.0); | |
| 8512 | |
| 8513 // Push registers conventionally. | |
| 8514 __ Push(x0, x1, x2, x3); | |
| 8515 __ Push(w4, w5, w6); | |
| 8516 __ Push(d0, d1); | |
| 8517 __ Push(s2); | |
| 8518 | |
| 8519 // Queue up a pop. | |
| 8520 queue.Queue(s2); | |
| 8521 | |
| 8522 queue.Queue(d1); | |
| 8523 queue.Queue(d0); | |
| 8524 | |
| 8525 queue.Queue(w6); | |
| 8526 queue.Queue(w5); | |
| 8527 queue.Queue(w4); | |
| 8528 | |
| 8529 queue.Queue(x3); | |
| 8530 queue.Queue(x2); | |
| 8531 queue.Queue(x1); | |
| 8532 queue.Queue(x0); | |
| 8533 | |
| 8534 Clobber(&masm, CPURegList(CPURegister::kRegister, kXRegSize, 0, 6)); | |
| 8535 Clobber(&masm, CPURegList(CPURegister::kFPRegister, kDRegSize, 0, 2)); | |
| 8536 | |
| 8537 // Actually pop them. | |
| 8538 queue.PopQueued(); | |
| 8539 | |
| 8540 __ Mov(csp, __ StackPointer()); | |
| 8541 __ SetStackPointer(csp); | |
| 8542 | |
| 8543 END(); | |
| 8544 | |
| 8545 RUN(); | |
| 8546 | |
| 8547 ASSERT_EQUAL_64(0x1234000000000000, x0); | |
| 8548 ASSERT_EQUAL_64(0x1234000100010001, x1); | |
| 8549 ASSERT_EQUAL_64(0x1234000200020002, x2); | |
| 8550 ASSERT_EQUAL_64(0x1234000300030003, x3); | |
| 8551 | |
| 8552 ASSERT_EQUAL_64(0x0000000012340004, x4); | |
| 8553 ASSERT_EQUAL_64(0x0000000012340005, x5); | |
| 8554 ASSERT_EQUAL_64(0x0000000012340006, x6); | |
| 8555 | |
| 8556 ASSERT_EQUAL_FP64(123400.0, d0); | |
| 8557 ASSERT_EQUAL_FP64(123401.0, d1); | |
| 8558 | |
| 8559 ASSERT_EQUAL_FP32(123402.0, s2); | |
| 8560 | |
| 8561 TEARDOWN(); | |
| 8562 } | |
| 8563 | |
| 8564 | |
| 8565 TEST(jump_both_smi) { | 8402 TEST(jump_both_smi) { |
| 8566 INIT_V8(); | 8403 INIT_V8(); |
| 8567 SETUP(); | 8404 SETUP(); |
| 8568 | 8405 |
| 8569 Label cond_pass_00, cond_pass_01, cond_pass_10, cond_pass_11; | 8406 Label cond_pass_00, cond_pass_01, cond_pass_10, cond_pass_11; |
| 8570 Label cond_fail_00, cond_fail_01, cond_fail_10, cond_fail_11; | 8407 Label cond_fail_00, cond_fail_01, cond_fail_10, cond_fail_11; |
| 8571 Label return1, return2, return3, done; | 8408 Label return1, return2, return3, done; |
| 8572 | 8409 |
| 8573 START(); | 8410 START(); |
| 8574 | 8411 |
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| 9628 AbsHelperX(-42); | 9465 AbsHelperX(-42); |
| 9629 AbsHelperX(kXMinInt); | 9466 AbsHelperX(kXMinInt); |
| 9630 AbsHelperX(kXMaxInt); | 9467 AbsHelperX(kXMaxInt); |
| 9631 | 9468 |
| 9632 AbsHelperW(0); | 9469 AbsHelperW(0); |
| 9633 AbsHelperW(42); | 9470 AbsHelperW(42); |
| 9634 AbsHelperW(-42); | 9471 AbsHelperW(-42); |
| 9635 AbsHelperW(kWMinInt); | 9472 AbsHelperW(kWMinInt); |
| 9636 AbsHelperW(kWMaxInt); | 9473 AbsHelperW(kWMaxInt); |
| 9637 } | 9474 } |
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