Subzero: Prototype to make use of RegNumT::No Register more concise

src/IceTargetLoweringX86BaseImpl.h

 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 873 matching lines @@
     Str << "%" << getRegName(Var->getRegNum(), VarType);
     return;
   }
   if (Var->mustHaveReg()) {
     llvm::report_fatal_error("Infinite-weight Variable (" + Var->getName(Func) +
                              ") has no register assigned - function " +
                              Func->getFunctionName());
   }
   const int32_t Offset = Var->getStackOffset();
   auto BaseRegNum = Var->getBaseRegNum();
-  if (BaseRegNum == RegNumT::NoRegister)
+  if (BaseRegNum.hasNoValue())
     BaseRegNum = getFrameOrStackReg();
   // Print in the form "Offset(%reg)", taking care that:
   //   - Offset is never printed when it is 0
 
   const bool DecorateAsm = Func->getContext()->getFlags().getDecorateAsm();
   // Only print Offset when it is nonzero, regardless of DecorateAsm.
   if (Offset) {
     if (DecorateAsm) {
       Str << Var->getSymbolicStackOffset(Func);
     } else {
       Str << Offset;
     }
   }
   const Type FrameSPTy = Traits::WordType;
   Str << "(%" << getRegName(BaseRegNum, FrameSPTy) << ")";
 }
 
 template <typename TraitsType>
 typename TargetX86Base<TraitsType>::X86Address
 TargetX86Base<TraitsType>::stackVarToAsmOperand(const Variable *Var) const {
   if (Var->hasReg())
     llvm::report_fatal_error("Stack Variable has a register assigned");
   if (Var->mustHaveReg()) {
     llvm::report_fatal_error("Infinite-weight Variable (" + Var->getName(Func) +
                              ") has no register assigned - function " +
                              Func->getFunctionName());
   }
   int32_t Offset = Var->getStackOffset();
   auto BaseRegNum = Var->getBaseRegNum();
-  if (Var->getBaseRegNum() == RegNumT::NoRegister)
+  if (Var->getBaseRegNum().hasNoValue())
     BaseRegNum = getFrameOrStackReg();
   return X86Address(Traits::getEncodedGPR(BaseRegNum), Offset,
                     AssemblerFixup::NoFixup);
 }
 
 template <typename TraitsType>
 void TargetX86Base<TraitsType>::addProlog(CfgNode *Node) {
   // Stack frame layout:
   //
   // +------------------------+
@@ skipping 181 matching lines @@
 
   emitGetIP(Node);
 
   const VarList &Args = Func->getArgs();
   size_t InArgsSizeBytes = 0;
   unsigned NumXmmArgs = 0;
   unsigned NumGPRArgs = 0;
   for (Variable *Arg : Args) {
     // Skip arguments passed in registers.
     if (isVectorType(Arg->getType())) {
-      if (Traits::getRegisterForXmmArgNum(NumXmmArgs) != RegNumT::NoRegister) {
+      if (Traits::getRegisterForXmmArgNum(NumXmmArgs).hasValue()) {
         ++NumXmmArgs;
         continue;
       }
     } else if (isScalarFloatingType(Arg->getType())) {
       if (Traits::X86_PASS_SCALAR_FP_IN_XMM &&
-          Traits::getRegisterForXmmArgNum(NumXmmArgs) != RegNumT::NoRegister) {
+          Traits::getRegisterForXmmArgNum(NumXmmArgs).hasValue()) {
         ++NumXmmArgs;
         continue;
       }
     } else {
       assert(isScalarIntegerType(Arg->getType()));
-      if (Traits::getRegisterForGprArgNum(Traits::WordType, NumGPRArgs) !=
-          RegNumT::NoRegister) {
+      if (Traits::getRegisterForGprArgNum(Traits::WordType, NumGPRArgs)
+              .hasValue()) {
         ++NumGPRArgs;
         continue;
       }
     }
     // For esp-based frames where the allocas are done outside the prolog, the
     // esp value may not stabilize to its home value until after all the
     // fixed-size alloca instructions have executed.  In this case, a stack
     // adjustment is needed when accessing in-args in order to copy them into
     // registers.
     size_t StackAdjBytes = 0;
@@ skipping 319 matching lines @@
   bool GprSlotsRemain = true;
 
   Context.init(Func->getEntryNode());
   Context.setInsertPoint(Context.getCur());
 
   for (SizeT i = 0, End = Args.size();
        i < End && (XmmSlotsRemain || GprSlotsRemain); ++i) {
     Variable *Arg = Args[i];
     Type Ty = Arg->getType();
     Variable *RegisterArg = nullptr;
-    auto RegNum = RegNumT::NoRegister;
+    RegNumT RegNum;
     if (isVectorType(Ty)) {
       RegNum = Traits::getRegisterForXmmArgNum(NumXmmArgs);
-      if (RegNum == RegNumT::NoRegister) {
+      if (RegNum.hasNoValue()) {
         XmmSlotsRemain = false;
         continue;
       }
       ++NumXmmArgs;
       RegisterArg = Func->makeVariable(Ty);
     } else if (isScalarFloatingType(Ty)) {
       if (!Traits::X86_PASS_SCALAR_FP_IN_XMM) {
         continue;
       }
       RegNum = Traits::getRegisterForXmmArgNum(NumXmmArgs);
-      if (RegNum == RegNumT::NoRegister) {
+      if (RegNum.hasNoValue()) {
         XmmSlotsRemain = false;
         continue;
       }
       ++NumXmmArgs;
       RegisterArg = Func->makeVariable(Ty);
     } else if (isScalarIntegerType(Ty)) {
       RegNum = Traits::getRegisterForGprArgNum(Ty, NumGprArgs);
-      if (RegNum == RegNumT::NoRegister) {
+      if (RegNum.hasNoValue()) {
         GprSlotsRemain = false;
         continue;
       }
       ++NumGprArgs;
       RegisterArg = Func->makeVariable(Ty);
     }
-    assert(RegNum != RegNumT::NoRegister);
+    assert(RegNum.hasValue());
     assert(RegisterArg != nullptr);
     // Replace Arg in the argument list with the home register. Then generate
     // an instruction in the prolog to copy the home register to the assigned
     // location of Arg.
     if (BuildDefs::dump())
       RegisterArg->setName(Func, "home_reg:" + Arg->getName(Func));
     RegisterArg->setRegNum(RegNum);
     RegisterArg->setIsArg();
     Arg->setIsArg(false);
 
@@ skipping 964 matching lines @@
   OperandList StackArgs, StackArgLocations;
   uint32_t ParameterAreaSizeBytes = 0;
 
   // Classify each argument operand according to the location where the argument
   // is passed.
   for (SizeT i = 0, NumArgs = Instr->getNumArgs(); i < NumArgs; ++i) {
     Operand *Arg = Instr->getArg(i);
     const Type Ty = Arg->getType();
     // The PNaCl ABI requires the width of arguments to be at least 32 bits.
     assert(typeWidthInBytes(Ty) >= 4);
-    if (isVectorType(Ty) && (Traits::getRegisterForXmmArgNum(XmmArgs.size()) !=
-                             RegNumT::NoRegister)) {
+    if (isVectorType(Ty) &&
+        Traits::getRegisterForXmmArgNum(XmmArgs.size()).hasValue()) {
       XmmArgs.push_back(Arg);
     } else if (isScalarFloatingType(Ty) && Traits::X86_PASS_SCALAR_FP_IN_XMM &&
-               (Traits::getRegisterForXmmArgNum(XmmArgs.size()) !=
-                RegNumT::NoRegister)) {
+               Traits::getRegisterForXmmArgNum(XmmArgs.size()).hasValue()) {
       XmmArgs.push_back(Arg);
     } else if (isScalarIntegerType(Ty) &&
-               (Traits::getRegisterForGprArgNum(Ty, GprArgs.size()) !=
-                RegNumT::NoRegister)) {
+               Traits::getRegisterForGprArgNum(Ty, GprArgs.size()).hasValue()) {
       GprArgs.emplace_back(Ty, Arg);
     } else {
       // Place on stack.
       StackArgs.push_back(Arg);
       if (isVectorType(Arg->getType())) {
         ParameterAreaSizeBytes =
             Traits::applyStackAlignment(ParameterAreaSizeBytes);
       }
       Variable *esp = getPhysicalRegister(getStackReg(), Traits::WordType);
       Constant *Loc = Ctx->getConstantInt32(ParameterAreaSizeBytes);
@@ skipping 4093 matching lines @@
   _psrl(Reg, Ctx->getConstantInt8(1));
   return Reg;
 }
 
 template <typename TraitsType>
 typename TargetX86Base<TraitsType>::X86OperandMem *
 TargetX86Base<TraitsType>::getMemoryOperandForStackSlot(Type Ty, Variable *Slot,
                                                         uint32_t Offset) {
   // Ensure that Loc is a stack slot.
   assert(Slot->mustNotHaveReg());
-  assert(Slot->getRegNum() == RegNumT::NoRegister);
+  assert(Slot->getRegNum().hasNoValue());
   // Compute the location of Loc in memory.
   // TODO(wala,stichnot): lea should not
   // be required. The address of the stack slot is known at compile time
   // (although not until after addProlog()).
   constexpr Type PointerType = IceType_i32;
   Variable *Loc = makeReg(PointerType);
   _lea(Loc, Slot);
   Constant *ConstantOffset = Ctx->getConstantInt32(Offset);
   return X86OperandMem::create(Func, Ty, Loc, ConstantOffset);
 }
 
 /// Lowering helper to copy a scalar integer source operand into some 8-bit GPR.
 /// Src is assumed to already be legalized.  If the source operand is known to
 /// be a memory or immediate operand, a simple mov will suffice.  But if the
 /// source operand can be a physical register, then it must first be copied into
 /// a physical register that is truncable to 8-bit, then truncated into a
 /// physical register that can receive a truncation, and finally copied into the
 /// result 8-bit register (which in general can be any 8-bit register).  For
 /// example, moving %ebp into %ah may be accomplished as:
 ///   movl %ebp, %edx
 ///   mov_trunc %edx, %dl  // this redundant assignment is ultimately elided
 ///   movb %dl, %ah
 /// On the other hand, moving a memory or immediate operand into ah:
 ///   movb 4(%ebp), %ah
 ///   movb $my_imm, %ah
 ///
 /// Note #1.  On a 64-bit target, the "movb 4(%ebp), %ah" is likely not
 /// encodable, so RegNum=Reg_ah should NOT be given as an argument.  Instead,
-/// use RegNum=NoRegister and then let the caller do a separate copy into
+/// use RegNum=RegNumT() and then let the caller do a separate copy into
 /// Reg_ah.
 ///
 /// Note #2.  ConstantRelocatable operands are also put through this process
 /// (not truncated directly) because our ELF emitter does R_386_32 relocations
 /// but not R_386_8 relocations.
 ///
 /// Note #3.  If Src is a Variable, the result will be an infinite-weight i8
 /// Variable with the RCX86_IsTrunc8Rcvr register class.  As such, this helper
 /// is a convenient way to prevent ah/bh/ch/dh from being an (invalid) argument
 /// to the pinsrb instruction.
@@ skipping 50 matching lines @@
   const bool UseNonsfi = Func->getContext()->getFlags().getUseNonsfi();
   const Type Ty = From->getType();
   // Assert that a physical register is allowed. To date, all calls to
   // legalize() allow a physical register. If a physical register needs to be
   // explicitly disallowed, then new code will need to be written to force a
   // spill.
   assert(Allowed & Legal_Reg);
   // If we're asking for a specific physical register, make sure we're not
   // allowing any other operand kinds. (This could be future work, e.g. allow
   // the shl shift amount to be either an immediate or in ecx.)
-  assert(RegNum == RegNumT::NoRegister || Allowed == Legal_Reg);
+  assert(RegNum.hasNoValue() || Allowed == Legal_Reg);
 
   // Substitute with an available infinite-weight variable if possible.  Only do
   // this when we are not asking for a specific register, and when the
   // substitution is not locked to a specific register, and when the types
   // match, in order to capture the vast majority of opportunities and avoid
   // corner cases in the lowering.
-  if (RegNum == RegNumT::NoRegister) {
+  if (RegNum.hasNoValue()) {
     if (Variable *Subst = getContext().availabilityGet(From)) {
       // At this point we know there is a potential substitution available.
       if (Subst->mustHaveReg() && !Subst->hasReg()) {
         // At this point we know the substitution will have a register.
         if (From->getType() == Subst->getType()) {
           // At this point we know the substitution's register is compatible.
           return Subst;
         }
       }
     }
@@ skipping 40 matching lines @@
         return From;
       Const = llvm::cast<Constant>(From);
     }
     // There should be no constants of vector type (other than undef).
     assert(!isVectorType(Ty));
 
     // If the operand is a 64 bit constant integer we need to legalize it to a
     // register in x86-64.
     if (Traits::Is64Bit) {
       if (llvm::isa<ConstantInteger64>(Const)) {
-        if (RegNum != RegNumT::NoRegister) {
+        if (RegNum.hasValue()) {
           assert(Traits::getGprForType(IceType_i64, RegNum) == RegNum);
         }
         return copyToReg(Const, RegNum);
       }
     }
 
     // If the operand is an 32 bit constant integer, we should check whether we
     // need to randomize it or pool it.
     if (auto *C = llvm::dyn_cast<ConstantInteger32>(Const)) {
       Operand *NewConst = randomizeOrPoolImmediate(C, RegNum);
@@ skipping 62 matching lines @@
     if (MustRematerialize) {
       assert(Ty == IceType_i32);
       Variable *NewVar = makeReg(Ty, RegNum);
       // Since Var is rematerializable, the offset will be added when the lea is
       // emitted.
       constexpr Constant *NoOffset = nullptr;
       auto *Mem = X86OperandMem::create(Func, Ty, Var, NoOffset);
       _lea(NewVar, Mem);
       From = NewVar;
     } else if ((!(Allowed & Legal_Mem) && !MustHaveRegister) ||
-               (RegNum != RegNumT::NoRegister && RegNum != Var->getRegNum())) {
+               (RegNum.hasValue() && RegNum != Var->getRegNum())) {
       From = copyToReg(From, RegNum);
     }
     return From;
   }
 
   llvm::report_fatal_error("Unhandled operand kind in legalize()");
   return From;
 }
 
 /// Provide a trivial wrapper to legalize() for this common usage.
@@ skipping 82 matching lines @@
   // randomization/pooling.
   return llvm::cast<X86OperandMem>(DoLegalize ? legalize(Mem)
                                               : randomizeOrPoolImmediate(Mem));
 }
 
 template <typename TraitsType>
 Variable *TargetX86Base<TraitsType>::makeReg(Type Type, RegNumT RegNum) {
   // There aren't any 64-bit integer registers for x86-32.
   assert(Traits::Is64Bit || Type != IceType_i64);
   Variable *Reg = Func->makeVariable(Type);
-  if (RegNum == RegNumT::NoRegister)
+  if (RegNum.hasValue())
+    Reg->setRegNum(RegNum);
+  else
     Reg->setMustHaveReg();
-  else
-    Reg->setRegNum(RegNum);
   return Reg;
 }
 
 template <typename TraitsType>
 const Type TargetX86Base<TraitsType>::TypeForSize[] = {
     IceType_i8, IceType_i16, IceType_i32, IceType_f64, IceType_v16i8};
 template <typename TraitsType>
 Type TargetX86Base<TraitsType>::largestTypeInSize(uint32_t Size,
                                                   uint32_t MaxSize) {
   assert(Size != 0);
@@ skipping 250 matching lines @@
     // TO:
     //  insert: mov $label, RegTemp
     //  insert: lea [base, RegTemp], RegTemp
     //  =>[RegTemp, index, shift]
 
     // Memory operand should never exist as source operands in phi lowering
     // assignments, so there is no need to reuse any registers here. For
     // phi lowering, we should not ask for new physical registers in
     // general. However, if we do meet Memory Operand during phi lowering,
     // we should not blind or pool the immediates for now.
-    if (RegNum != RegNumT::NoRegister)
+    if (RegNum.hasValue())
       return MemOperand;
     Variable *RegTemp = makeReg(IceType_i32);
     IceString Label;
     llvm::raw_string_ostream Label_stream(Label);
     MemOperand->getOffset()->emitPoolLabel(Label_stream, Ctx);
     MemOperand->getOffset()->setShouldBePooled(true);
     constexpr RelocOffsetT SymOffset = 0;
     constexpr bool SuppressMangling = true;
     Constant *Symbol =
         Ctx->getConstantSym(SymOffset, Label_stream.str(), SuppressMangling);
@@ skipping 164 matching lines @@
         emitGlobal(*Var, SectionSuffix);
       }
     }
   } break;
   }
 }
 } // end of namespace X86NAMESPACE
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H