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1 //===- subzero/src/IceTargetLoweringX8632Traits.h - x86-32 traits -*- C++ -*-=// | 1 //===- subzero/src/IceTargetLoweringX8632Traits.h - x86-32 traits -*- C++ -*-=// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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368 case IceType_i16: | 368 case IceType_i16: |
369 return RegisterSet::Reg_ax; | 369 return RegisterSet::Reg_ax; |
370 case IceType_i32: | 370 case IceType_i32: |
371 return RegisterSet::Reg_eax; | 371 return RegisterSet::Reg_eax; |
372 } | 372 } |
373 } | 373 } |
374 | 374 |
375 public: | 375 public: |
376 // Return a register in RegNum's alias set that is suitable for Ty. | 376 // Return a register in RegNum's alias set that is suitable for Ty. |
377 static RegNumT getGprForType(Type Ty, RegNumT RegNum) { | 377 static RegNumT getGprForType(Type Ty, RegNumT RegNum) { |
378 assert(RegNum != RegNumT::NoRegister); | 378 assert(RegNum.hasValue()); |
379 | 379 |
380 if (!isScalarIntegerType(Ty)) { | 380 if (!isScalarIntegerType(Ty)) { |
381 return RegNum; | 381 return RegNum; |
382 } | 382 } |
383 | 383 |
384 // [abcd]h registers are not convertible to their ?l, ?x, and e?x versions. | 384 // [abcd]h registers are not convertible to their ?l, ?x, and e?x versions. |
385 switch (RegNum) { | 385 switch (RegNum) { |
386 default: | 386 default: |
387 break; | 387 break; |
388 case RegisterSet::Reg_ah: | 388 case RegisterSet::Reg_ah: |
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679 /// The maximum number of arguments to pass in GPR registers | 679 /// The maximum number of arguments to pass in GPR registers |
680 static constexpr uint32_t X86_MAX_GPR_ARGS = 0; | 680 static constexpr uint32_t X86_MAX_GPR_ARGS = 0; |
681 /// Whether scalar floating point arguments are passed in XMM registers | 681 /// Whether scalar floating point arguments are passed in XMM registers |
682 static constexpr bool X86_PASS_SCALAR_FP_IN_XMM = false; | 682 static constexpr bool X86_PASS_SCALAR_FP_IN_XMM = false; |
683 /// Get the register for a given argument slot in the XMM registers. | 683 /// Get the register for a given argument slot in the XMM registers. |
684 static RegNumT getRegisterForXmmArgNum(uint32_t ArgNum) { | 684 static RegNumT getRegisterForXmmArgNum(uint32_t ArgNum) { |
685 // TODO(sehr): Change to use the CCArg technique used in ARM32. | 685 // TODO(sehr): Change to use the CCArg technique used in ARM32. |
686 static_assert(RegisterSet::Reg_xmm0 + 1 == RegisterSet::Reg_xmm1, | 686 static_assert(RegisterSet::Reg_xmm0 + 1 == RegisterSet::Reg_xmm1, |
687 "Inconsistency between XMM register numbers and ordinals"); | 687 "Inconsistency between XMM register numbers and ordinals"); |
688 if (ArgNum >= X86_MAX_XMM_ARGS) { | 688 if (ArgNum >= X86_MAX_XMM_ARGS) { |
689 return RegNumT::NoRegister; | 689 return RegNumT(); |
690 } | 690 } |
691 return RegNumT::fixme(RegisterSet::Reg_xmm0 + ArgNum); | 691 return RegNumT::fixme(RegisterSet::Reg_xmm0 + ArgNum); |
692 } | 692 } |
693 /// Get the register for a given argument slot in the GPRs. | 693 /// Get the register for a given argument slot in the GPRs. |
694 static RegNumT getRegisterForGprArgNum(Type Ty, uint32_t ArgNum) { | 694 static RegNumT getRegisterForGprArgNum(Type Ty, uint32_t ArgNum) { |
695 assert(Ty == IceType_i64 || Ty == IceType_i32); | 695 assert(Ty == IceType_i64 || Ty == IceType_i32); |
696 (void)Ty; | 696 (void)Ty; |
697 (void)ArgNum; | 697 (void)ArgNum; |
698 return RegNumT::NoRegister; | 698 return RegNumT(); |
699 } | 699 } |
700 | 700 |
701 /// The number of bits in a byte | 701 /// The number of bits in a byte |
702 static constexpr uint32_t X86_CHAR_BIT = 8; | 702 static constexpr uint32_t X86_CHAR_BIT = 8; |
703 /// Stack alignment. This is defined in IceTargetLoweringX8632.cpp because it | 703 /// Stack alignment. This is defined in IceTargetLoweringX8632.cpp because it |
704 /// is used as an argument to std::max(), and the default std::less<T> has an | 704 /// is used as an argument to std::max(), and the default std::less<T> has an |
705 /// operator(T const&, T const&) which requires this member to have an | 705 /// operator(T const&, T const&) which requires this member to have an |
706 /// address. | 706 /// address. |
707 static const uint32_t X86_STACK_ALIGNMENT_BYTES; | 707 static const uint32_t X86_STACK_ALIGNMENT_BYTES; |
708 /// Size of the return address on the stack | 708 /// Size of the return address on the stack |
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991 | 991 |
992 static uint8_t InstSegmentPrefixes[]; | 992 static uint8_t InstSegmentPrefixes[]; |
993 }; | 993 }; |
994 | 994 |
995 using Traits = ::Ice::X8632::TargetX8632Traits; | 995 using Traits = ::Ice::X8632::TargetX8632Traits; |
996 } // end of namespace X8632 | 996 } // end of namespace X8632 |
997 | 997 |
998 } // end of namespace Ice | 998 } // end of namespace Ice |
999 | 999 |
1000 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8632TRAITS_H | 1000 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8632TRAITS_H |
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