Subzero: Prototype to make use of RegNumT::No Register more concise

src/IceTargetLoweringMIPS32.cpp

 //===- subzero/src/IceTargetLoweringMIPS32.cpp - MIPS32 lowering ----------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 342 matching lines @@
       UnimplementedError(Func->getContext()->getFlags());
     return Ctx->getConstantZero(Ty);
   }
   return From;
 }
 
 Variable *TargetMIPS32::makeReg(Type Type, RegNumT RegNum) {
   // There aren't any 64-bit integer registers for Mips32.
   assert(Type != IceType_i64);
   Variable *Reg = Func->makeVariable(Type);
-  if (RegNum == RegNumT::NoRegister)
+  if (RegNum.hasValue())
+    Reg->setRegNum(RegNum);
+  else
     Reg->setMustHaveReg();
-  else
-    Reg->setRegNum(RegNum);
   return Reg;
 }
 
 void TargetMIPS32::emitVariable(const Variable *Var) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Ctx->getStrEmit();
   const Type FrameSPTy = IceType_i32;
   if (Var->hasReg()) {
     Str << '$' << getRegName(Var->getRegNum(), Var->getType());
@@ skipping 869 matching lines @@
     Context.insert<InstFakeDef>(Reg);
     return Reg;
   } else if (auto *C32 = llvm::dyn_cast<ConstantInteger32>(From)) {
     const uint32_t Value = C32->getValue();
     // Check if the immediate will fit in a Flexible second operand,
     // if a Flexible second operand is allowed. We need to know the exact
     // value, so that rules out relocatable constants.
     // Also try the inverse and use MVN if possible.
     // Do a movw/movt to a register.
     Variable *Reg;
-    if (RegNum == RegNumT::NoRegister)
+    if (RegNum.hasValue())
+      Reg = getPhysicalRegister(RegNum);
+    else
       Reg = makeReg(Ty, RegNum);
-    else
-      Reg = getPhysicalRegister(RegNum);
     if (isInt<16>(int32_t(Value))) {
       Variable *Zero = getPhysicalRegister(RegMIPS32::Reg_ZERO, Ty);
       Context.insert<InstFakeDef>(Zero);
       _addiu(Reg, Zero, Value);
     } else {
       uint32_t UpperBits = (Value >> 16) & 0xFFFF;
       (void)UpperBits;
       uint32_t LowerBits = Value & 0xFFFF;
       Variable *TReg = makeReg(Ty, RegNum);
       _lui(TReg, UpperBits);
       _ori(Reg, TReg, LowerBits);
     }
     return Reg;
   }
   if (auto *Var = llvm::dyn_cast<Variable>(From)) {
     // Check if the variable is guaranteed a physical register.  This
     // can happen either when the variable is pre-colored or when it is
     // assigned infinite weight.
     bool MustHaveRegister = (Var->hasReg() || Var->mustHaveReg());
     // We need a new physical register for the operand if:
     //   Mem is not allowed and Var isn't guaranteed a physical
     //   register, or
     //   RegNum is required and Var->getRegNum() doesn't match.
     if ((!(Allowed & Legal_Mem) && !MustHaveRegister) ||
-        (RegNum != RegNumT::NoRegister && RegNum != Var->getRegNum())) {
+        (RegNum.hasValue() && RegNum != Var->getRegNum())) {
       From = copyToReg(From, RegNum);
     }
     return From;
   }
   return From;
 }
 
 TargetHeaderMIPS32::TargetHeaderMIPS32(GlobalContext *Ctx)
     : TargetHeaderLowering(Ctx) {}
 
 void TargetHeaderMIPS32::lower() {
   OstreamLocker L(Ctx);
   Ostream &Str = Ctx->getStrEmit();
   Str << "\t.set\t"
       << "nomicromips\n";
   Str << "\t.set\t"
       << "nomips16\n";
 }
 
 llvm::SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM];
 llvm::SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM];
 llvm::SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM];
 
 } // end of namespace MIPS32
 } // end of namespace Ice