Subzero: Prototype to make use of RegNumT::No Register more concise

src/IceTargetLoweringARM32.h

 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 156 matching lines @@
   enum OperandLegalization {
     Legal_Reg = 1 << 0,  /// physical register, not stack location
     Legal_Flex = 1 << 1, /// A flexible operand2, which can hold rotated small
                          /// immediates, shifted registers, or modified fp imm.
     Legal_Mem = 1 << 2,  /// includes [r0, r1 lsl #2] as well as [sp, #12]
     Legal_Rematerializable = 1 << 3,
     Legal_Default = ~Legal_Rematerializable,
   };
 
   using LegalMask = uint32_t;
-  Operand *legalizeUndef(Operand *From, RegNumT RegNum = RegNumT::NoRegister);
+  Operand *legalizeUndef(Operand *From, RegNumT RegNum = RegNumT());
   Operand *legalize(Operand *From, LegalMask Allowed = Legal_Default,
-                    RegNumT RegNum = RegNumT::NoRegister);
-  Variable *legalizeToReg(Operand *From, RegNumT RegNum = RegNumT::NoRegister);
+                    RegNumT RegNum = RegNumT());
+  Variable *legalizeToReg(Operand *From, RegNumT RegNum = RegNumT());
 
   OperandARM32ShAmtImm *shAmtImm(uint32_t ShAmtImm) const {
     assert(ShAmtImm < 32);
     return OperandARM32ShAmtImm::create(
         Func,
         llvm::cast<ConstantInteger32>(Ctx->getConstantInt32(ShAmtImm & 0x1F)));
   }
 
   GlobalContext *getCtx() const { return Ctx; }
 
@@ skipping 72 matching lines @@
   uint32_t getCallStackArgumentsSizeBytes(const InstCall *Instr) override;
   void genTargetHelperCallFor(Inst *Instr) override;
   void doAddressOptLoad() override;
   void doAddressOptStore() override;
   void randomlyInsertNop(float Probability,
                          RandomNumberGenerator &RNG) override;
 
   OperandARM32Mem *formMemoryOperand(Operand *Ptr, Type Ty);
 
   Variable64On32 *makeI64RegPair();
-  Variable *makeReg(Type Ty, RegNumT RegNum = RegNumT::NoRegister);
+  Variable *makeReg(Type Ty, RegNumT RegNum = RegNumT());
   static Type stackSlotType();
-  Variable *copyToReg(Operand *Src, RegNumT RegNum = RegNumT::NoRegister);
+  Variable *copyToReg(Operand *Src, RegNumT RegNum = RegNumT());
   void alignRegisterPow2(Variable *Reg, uint32_t Align,
-                         RegNumT TmpRegNum = RegNumT::NoRegister);
+                         RegNumT TmpRegNum = RegNumT());
 
   /// Returns a vector in a register with the given constant entries.
-  Variable *makeVectorOfZeros(Type Ty, RegNumT RegNum = RegNumT::NoRegister);
+  Variable *makeVectorOfZeros(Type Ty, RegNumT RegNum = RegNumT());
 
   void
   makeRandomRegisterPermutation(llvm::SmallVectorImpl<RegNumT> &Permutation,
                                 const llvm::SmallBitVector &ExcludeRegisters,
                                 uint64_t Salt) const override;
 
   // If a divide-by-zero check is needed, inserts a: test; branch .LSKIP; trap;
   // .LSKIP: <continuation>. If no check is needed nothing is inserted.
   void div0Check(Type Ty, Operand *SrcLo, Operand *SrcHi);
   using ExtInstr = void (TargetARM32::*)(Variable *, Variable *,
@@ skipping 994 matching lines @@
 private:
   ~TargetHeaderARM32() = default;
 
   TargetARM32Features CPUFeatures;
 };
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H