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1 //===- subzero/src/IceRegAlloc.h - Linear-scan reg. allocation --*- C++ -*-===// | 1 //===- subzero/src/IceRegAlloc.h - Linear-scan reg. allocation --*- C++ -*-===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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51 using DefUseErrorList = llvm::SmallVector<SizeT, 10>; | 51 using DefUseErrorList = llvm::SmallVector<SizeT, 10>; |
52 | 52 |
53 class IterationState { | 53 class IterationState { |
54 IterationState(const IterationState &) = delete; | 54 IterationState(const IterationState &) = delete; |
55 IterationState operator=(const IterationState &) = delete; | 55 IterationState operator=(const IterationState &) = delete; |
56 | 56 |
57 public: | 57 public: |
58 IterationState() = default; | 58 IterationState() = default; |
59 Variable *Cur = nullptr; | 59 Variable *Cur = nullptr; |
60 Variable *Prefer = nullptr; | 60 Variable *Prefer = nullptr; |
61 RegNumT PreferReg = RegNumT::NoRegister; | 61 RegNumT PreferReg; |
62 bool AllowOverlap = false; | 62 bool AllowOverlap = false; |
63 llvm::SmallBitVector RegMask; | 63 llvm::SmallBitVector RegMask; |
64 llvm::SmallBitVector RegMaskUnfiltered; | 64 llvm::SmallBitVector RegMaskUnfiltered; |
65 llvm::SmallBitVector Free; | 65 llvm::SmallBitVector Free; |
66 llvm::SmallBitVector FreeUnfiltered; | 66 llvm::SmallBitVector FreeUnfiltered; |
67 llvm::SmallBitVector PrecoloredUnhandledMask; // Note: only used for dumping | 67 llvm::SmallBitVector PrecoloredUnhandledMask; // Note: only used for dumping |
68 llvm::SmallVector<RegWeight, REGS_SIZE> Weights; | 68 llvm::SmallVector<RegWeight, REGS_SIZE> Weights; |
69 }; | 69 }; |
70 | 70 |
71 bool livenessValidateIntervals(const DefUseErrorList &DefsWithoutUses, | 71 bool livenessValidateIntervals(const DefUseErrorList &DefsWithoutUses, |
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131 bool FindPreference = false; | 131 bool FindPreference = false; |
132 bool FindOverlap = false; | 132 bool FindOverlap = false; |
133 | 133 |
134 const bool Verbose; | 134 const bool Verbose; |
135 const bool UseReserve; | 135 const bool UseReserve; |
136 }; | 136 }; |
137 | 137 |
138 } // end of namespace Ice | 138 } // end of namespace Ice |
139 | 139 |
140 #endif // SUBZERO_SRC_ICEREGALLOC_H | 140 #endif // SUBZERO_SRC_ICEREGALLOC_H |
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