Subzero: Prototype to make use of RegNumT::No Register more concise

src/IceInstARM32.h

 //===- subzero/src/IceInstARM32.h - ARM32 machine instructions --*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 343 matching lines @@
   static bool classof(const Operand *Operand) {
     return Operand->getKind() == StackVariableKind;
   }
   void setBaseRegNum(RegNumT RegNum) { BaseRegNum = RegNum; }
   RegNumT getBaseRegNum() const override { return BaseRegNum; }
   // Inherit dump() and emit() from Variable.
 
 private:
   StackVariable(Type Ty, SizeT Index)
       : Variable(StackVariableKind, Ty, Index) {}
-  RegNumT BaseRegNum = RegNumT::NoRegister;
+  RegNumT BaseRegNum;
 };
 
 /// Base class for ARM instructions. While most ARM instructions can be
 /// conditionally executed, a few of them are not predicable (halt, memory
 /// barriers, etc.).
 class InstARM32 : public InstTarget {
   InstARM32() = delete;
   InstARM32(const InstARM32 &) = delete;
   InstARM32 &operator=(const InstARM32 &) = delete;
 
@@ skipping 1148 matching lines @@
 // violations and link errors.
 
 template <> void InstARM32Ldr::emit(const Cfg *Func) const;
 template <> void InstARM32Movw::emit(const Cfg *Func) const;
 template <> void InstARM32Movt::emit(const Cfg *Func) const;
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEINSTARM32_H