Fix missing register class.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 260 matching lines @@
     ;
 std::array<RegNumT, NumVec128Args> Vec128ArgInitializer;
 
 IceString getRegClassName(RegClass C) {
   auto ClassNum = static_cast<RegARM32::RegClassARM32>(C);
   assert(ClassNum < RegARM32::RCARM32_NUM);
   switch (ClassNum) {
   default:
     assert(C < RC_Target);
     return regClassString(C);
-    // Add handling of new register classes below.
+  // Add handling of new register classes below.
+  case RegARM32::RCARM32_QtoS:
+    return "QtoS";
   }
 }
 
 } // end of anonymous namespace
 
 TargetARM32::TargetARM32(Cfg *Func)
     : TargetLowering(Func), NeedSandboxing(SandboxingType == ST_NaCl),
       CPUFeatures(Func->getContext()->getFlags()) {}
 
 void TargetARM32::staticInit(GlobalContext *Ctx) {
@@ skipping 6291 matching lines @@
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM];
 llvm::SmallBitVector
     TargetARM32::TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM];
 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 
 } // end of namespace ARM32
 } // end of namespace Ice