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1 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===// | 1 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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271 ; | 271 ; |
272 std::array<RegNumT, NumVec128Args> Vec128ArgInitializer; | 272 std::array<RegNumT, NumVec128Args> Vec128ArgInitializer; |
273 | 273 |
274 IceString getRegClassName(RegClass C) { | 274 IceString getRegClassName(RegClass C) { |
275 auto ClassNum = static_cast<RegARM32::RegClassARM32>(C); | 275 auto ClassNum = static_cast<RegARM32::RegClassARM32>(C); |
276 assert(ClassNum < RegARM32::RCARM32_NUM); | 276 assert(ClassNum < RegARM32::RCARM32_NUM); |
277 switch (ClassNum) { | 277 switch (ClassNum) { |
278 default: | 278 default: |
279 assert(C < RC_Target); | 279 assert(C < RC_Target); |
280 return regClassString(C); | 280 return regClassString(C); |
281 // Add handling of new register classes below. | 281 // Add handling of new register classes below. |
| 282 case RegARM32::RCARM32_QtoS: |
| 283 return "QtoS"; |
282 } | 284 } |
283 } | 285 } |
284 | 286 |
285 } // end of anonymous namespace | 287 } // end of anonymous namespace |
286 | 288 |
287 TargetARM32::TargetARM32(Cfg *Func) | 289 TargetARM32::TargetARM32(Cfg *Func) |
288 : TargetLowering(Func), NeedSandboxing(SandboxingType == ST_NaCl), | 290 : TargetLowering(Func), NeedSandboxing(SandboxingType == ST_NaCl), |
289 CPUFeatures(Func->getContext()->getFlags()) {} | 291 CPUFeatures(Func->getContext()->getFlags()) {} |
290 | 292 |
291 void TargetARM32::staticInit(GlobalContext *Ctx) { | 293 void TargetARM32::staticInit(GlobalContext *Ctx) { |
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6583 Str << ".eabi_attribute 14, 3 @ Tag_ABI_PCS_R9_use: Not used\n"; | 6585 Str << ".eabi_attribute 14, 3 @ Tag_ABI_PCS_R9_use: Not used\n"; |
6584 } | 6586 } |
6585 | 6587 |
6586 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM]; | 6588 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM]; |
6587 llvm::SmallBitVector | 6589 llvm::SmallBitVector |
6588 TargetARM32::TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM]; | 6590 TargetARM32::TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM]; |
6589 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM]; | 6591 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM]; |
6590 | 6592 |
6591 } // end of namespace ARM32 | 6593 } // end of namespace ARM32 |
6592 } // end of namespace Ice | 6594 } // end of namespace Ice |
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