ARM32 vector lowering: fabs, scalarize remaining arithmetic operations.

tests_lit/assembler/arm32/div-vec.ll

Index: tests_lit/assembler/arm32/div-vec.ll
diff --git a/tests_lit/assembler/arm32/udiv-vec.ll b/tests_lit/assembler/arm32/div-vec.ll
similarity index 67%
rename from tests_lit/assembler/arm32/udiv-vec.ll
rename to tests_lit/assembler/arm32/div-vec.ll
index 086cadfeb4c92478789d3d986ef9bcade0c221df..91b953bcd8866f726c5869b593f495fa76f4bc0a 100644
--- a/tests_lit/assembler/arm32/udiv-vec.ll
+++ b/tests_lit/assembler/arm32/div-vec.ll
@@ -248,3 +248,120 @@ entry:
 
   ret <16 x i8> %res
 }
+
+define internal <4 x i32> @testSdiv4i32(<4 x i32> %v1, <4 x i32> %v2) {
+; ASM-LABEL: testSdiv4i32:
+; IASM-LABEL: testSdiv4i32:
+
+entry:
+  %res = sdiv <4 x i32> %v1, %v2
+
+; ASM:     sdiv r0, r0, r1
+; ASM:     sdiv r0, r0, r1
+; ASM:     sdiv r0, r0, r1
+; ASM:     sdiv r0, r0, r1
+
+; IASM-NOT:     sdiv
+
+  ret <4 x i32> %res
+}
+
+define internal <8 x i16> @testSdiv8i16(<8 x i16> %v1, <8 x i16> %v2) {
+; ASM-LABEL: testSdiv8i16:
+; IASM-LABEL: testSdiv8i16:
+
+entry:
+  %res = sdiv <8 x i16> %v1, %v2
+
+; ASM:     sxth            r0, r0
+; ASM:     sxth            r1, r1
+; ASM:     sdiv r0, r0, r1
+; ASM:     sxth            r0, r0
+; ASM:     sxth            r1, r1
+; ASM:     sdiv r0, r0, r1
+; ASM:     sxth            r0, r0
+; ASM:     sxth            r1, r1
+; ASM:     sdiv r0, r0, r1
+; ASM:     sxth            r0, r0
+; ASM:     sxth            r1, r1
+; ASM:     sdiv r0, r0, r1
+; ASM:     sxth            r0, r0
+; ASM:     sxth            r1, r1
+; ASM:     sdiv r0, r0, r1
+; ASM:     sxth            r0, r0
+; ASM:     sxth            r1, r1
+; ASM:     sdiv r0, r0, r1
+; ASM:     sxth            r0, r0
+; ASM:     sxth            r1, r1
+; ASM:     sdiv r0, r0, r1
+; ASM:     sxth            r0, r0
+; ASM:     sxth            r1, r1
+; ASM:     sdiv r0, r0, r1
+
+; IASM-NOT:     sxth
+; IASM-NOT:     sdiv
+
+  ret <8 x i16> %res
+}
+
+define internal <16 x i8> @testSdiv16i8(<16 x i8> %v1, <16 x i8> %v2) {
+; ASM-LABEL: testSdiv16i8:
+; IASM-LABEL: testSdiv16i8:
+
+entry:
+  %res = sdiv <16 x i8> %v1, %v2
+
+; ASM:     sxtb            r0, r0
+; ASM:     sxtb            r1, r1
+; ASM:     sdiv r0, r0, r1
+; ASM:     sxtb            r0, r0
+; ASM:     sxtb            r1, r1
+; ASM:     sdiv r0, r0, r1
+; ASM:     sxtb            r0, r0
+; ASM:     sxtb            r1, r1
+; ASM:     sdiv r0, r0, r1
+; ASM:     sxtb            r0, r0
+; ASM:     sxtb            r1, r1
+; ASM:     sdiv r0, r0, r1
+; ASM:     sxtb            r0, r0
+; ASM:     sxtb            r1, r1
+; ASM:     sdiv r0, r0, r1
+; ASM:     sxtb            r0, r0
+; ASM:     sxtb            r1, r1
+; ASM:     sdiv r0, r0, r1
+; ASM:     sxtb            r0, r0
+; ASM:     sxtb            r1, r1
+; ASM:     sdiv r0, r0, r1
+; ASM:     sxtb            r0, r0
+; ASM:     sxtb            r1, r1
+; ASM:     sdiv r0, r0, r1
+; ASM:     sxtb            r0, r0
+; ASM:     sxtb            r1, r1
+; ASM:     sdiv r0, r0, r1
+; ASM:     sxtb            r0, r0
+; ASM:     sxtb            r1, r1
+; ASM:     sdiv r0, r0, r1
+; ASM:     sxtb            r0, r0
+; ASM:     sxtb            r1, r1
+; ASM:     sdiv r0, r0, r1
+; ASM:     sxtb            r0, r0
+; ASM:     sxtb            r1, r1
+; ASM:     sdiv r0, r0, r1
+; ASM:     sxtb            r0, r0
+; ASM:     sxtb            r1, r1
+; ASM:     sdiv r0, r0, r1
+; ASM:     sxtb            r0, r0
+; ASM:     sxtb            r1, r1
+; ASM:     sdiv r0, r0, r1
+; ASM:     sxtb            r0, r0
+; ASM:     sxtb            r1, r1
+; ASM:     sdiv r0, r0, r1
+; ASM:     sxtb            r0, r0
+; ASM:     sxtb            r1, r1
+; ASM:     sdiv r0, r0, r1
+
+; IASM-NOT:     sxtb
+; IASM-NOT:     sdiv
+
+  ret <16 x i8> %res
+}