Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(273)

Issues Search
    My Issues | Starred     Open | Closed | All

Side by Side Diff: tests_lit/assembler/arm32/udiv-vec.ll

Issue 1685253003: ARM32 vector lowering: fabs, scalarize remaining arithmetic operations. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: More tests. Enabling crosstests. Created 4 years, 10 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch
« tests_lit/assembler/arm32/rem-vec.ll ('K') | « tests_lit/assembler/arm32/rem-vec.ll ('k') | tests_lit/assembler/arm32/vabs.ll » ('j') | tests_lit/assembler/arm32/vabs.ll » ('J')
Toggle Intra-line Diffs ('i') | Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
OLDNEW
(Empty)
1 ; Show that we know how to translate vector division instructions.
2
3 ; REQUIRES: allow_dump
4
5 ; Compile using standalone assembler.
6 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 -mattr=hwdiv-arm \
7 ; RUN: | FileCheck %s --check-prefix=ASM
8
9 ; Show bytes in assembled standalone code.
10 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
11 ; RUN: --args -O2 -mattr=hwdiv-arm \
12 ; RUN: | FileCheck %s --check-prefix=DIS
13
14 ; Compile using integrated assembler.
15 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 -mattr=hwdiv-arm \
16 ; RUN: | FileCheck %s --check-prefix=IASM
17
18 ; Show bytes in assembled integrated code.
19 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
20 ; RUN: --args -O2 -mattr=hwdiv-arm \
21 ; RUN: | FileCheck %s --check-prefix=DIS
22
23 define internal <4 x float> @testVdivFloat4(<4 x float> %v1, <4 x float> %v2) {
24 ; ASM-LABEL: testVdivFloat4:
25 ; DIS-LABEL: 00000000 <testVdivFloat4>:
26 ; IASM-LABEL: testVdivFloat4:
27
28 entry:
29 %res = fdiv <4 x float> %v1, %v2
30
31 ; TODO(eholk): this code could be a lot better. Fix the code generator
32 ; and update the test. Same for the rest of the tests.
33
34 ; ASM: vdiv.f32 s12, s12, s13
35 ; ASM-NEXT: vmov.f32 s8, s12
36 ; ASM: vdiv.f32 s12, s12, s13
37 ; ASM-NEXT: vmov.f32 s9, s12
38 ; ASM: vdiv.f32 s12, s12, s13
39 ; ASM-NEXT: vmov.f32 s10, s12
40 ; ASM: vdiv.f32 s0, s0, s4
41 ; ASM-NEXT: vmov.f32 s11, s0
42
43 ; DIS: 8: ee866a26
44 ; DIS: 18: ee866a26
45 ; DIS: 28: ee866a26
46 ; DIS: 38: ee800a02
47
48 ; IASM-NOT: vdiv
49
50 ret <4 x float> %res
51 }
52
53 define internal <4 x i32> @testVdiv4i32(<4 x i32> %v1, <4 x i32> %v2) {
54 ; ASM-LABEL: testVdiv4i32:
55 ; DIS-LABEL: 00000050 <testVdiv4i32>:
56 ; IASM-LABEL: testVdiv4i32:
57
58 entry:
59 %res = udiv <4 x i32> %v1, %v2
60
61 ; ASM: udiv r0, r0, r1
62 ; ASM: udiv r0, r0, r1
63 ; ASM: udiv r0, r0, r1
64 ; ASM: udiv r0, r0, r1
65
66 ; DIS: 64: e730f110
67 ; DIS: 80: e730f110
68 ; DIS: 9c: e730f110
69 ; DIS: b8: e730f110
70
71 ; IASM-NOT: udiv
72
73 ret <4 x i32> %res
74 }
75
76 define internal <8 x i16> @testVdiv8i16(<8 x i16> %v1, <8 x i16> %v2) {
77 ; ASM-LABEL: testVdiv8i16:
78 ; DIS-LABEL: 000000d0 <testVdiv8i16>:
79 ; IASM-LABEL: testVdiv8i16:
80
81 entry:
82 %res = udiv <8 x i16> %v1, %v2
83
84 ; ASM: uxth r0, r0
85 ; ASM: uxth r1, r1
86 ; ASM: udiv r0, r0, r1
87 ; ASM: uxth r0, r0
88 ; ASM: uxth r1, r1
89 ; ASM: udiv r0, r0, r1
90 ; ASM: uxth r0, r0
91 ; ASM: uxth r1, r1
92 ; ASM: udiv r0, r0, r1
93 ; ASM: uxth r0, r0
94 ; ASM: uxth r1, r1
95 ; ASM: udiv r0, r0, r1
96 ; ASM: uxth r0, r0
97 ; ASM: uxth r1, r1
98 ; ASM: udiv r0, r0, r1
99 ; ASM: uxth r0, r0
100 ; ASM: uxth r1, r1
101 ; ASM: udiv r0, r0, r1
102 ; ASM: uxth r0, r0
103 ; ASM: uxth r1, r1
104 ; ASM: udiv r0, r0, r1
105 ; ASM: uxth r0, r0
106 ; ASM: uxth r1, r1
107 ; ASM: udiv r0, r0, r1
108
109 ; DIS: e4: e6ff0070
110 ; DIS: e8: e6ff1071
111 ; DIS: ec: e730f110
112 ; DIS: 108: e6ff0070
113 ; DIS: 10c: e6ff1071
114 ; DIS: 110: e730f110
115 ; DIS: 12c: e6ff0070
116 ; DIS: 130: e6ff1071
117 ; DIS: 134: e730f110
118 ; DIS: 150: e6ff0070
119 ; DIS: 154: e6ff1071
120 ; DIS: 158: e730f110
121 ; DIS: 174: e6ff0070
122 ; DIS: 178: e6ff1071
123 ; DIS: 17c: e730f110
124 ; DIS: 198: e6ff0070
125 ; DIS: 19c: e6ff1071
126 ; DIS: 1a0: e730f110
127 ; DIS: 1bc: e6ff0070
128 ; DIS: 1c0: e6ff1071
129 ; DIS: 1c4: e730f110
130 ; DIS: 1e0: e6ff0070
131 ; DIS: 1e4: e6ff1071
132 ; DIS: 1e8: e730f110
133
134 ; IASM-NOT: uxth
135 ; IASM-NOT: udiv
136
137 ret <8 x i16> %res
138 }
139
140 define internal <16 x i8> @testVdiv16i8(<16 x i8> %v1, <16 x i8> %v2) {
141 ; ASM-LABEL: testVdiv16i8:
142 ; DIS-LABEL: 00000200 <testVdiv16i8>:
143 ; IASM-LABEL: testVdiv16i8:
144
145 entry:
146 %res = udiv <16 x i8> %v1, %v2
147
148 ; ASM: uxtb r0, r0
149 ; ASM: uxtb r1, r1
150 ; ASM: udiv r0, r0, r1
151 ; ASM: uxtb r0, r0
152 ; ASM: uxtb r1, r1
153 ; ASM: udiv r0, r0, r1
154 ; ASM: uxtb r0, r0
155 ; ASM: uxtb r1, r1
156 ; ASM: udiv r0, r0, r1
157 ; ASM: uxtb r0, r0
158 ; ASM: uxtb r1, r1
159 ; ASM: udiv r0, r0, r1
160 ; ASM: uxtb r0, r0
161 ; ASM: uxtb r1, r1
162 ; ASM: udiv r0, r0, r1
163 ; ASM: uxtb r0, r0
164 ; ASM: uxtb r1, r1
165 ; ASM: udiv r0, r0, r1
166 ; ASM: uxtb r0, r0
167 ; ASM: uxtb r1, r1
168 ; ASM: udiv r0, r0, r1
169 ; ASM: uxtb r0, r0
170 ; ASM: uxtb r1, r1
171 ; ASM: udiv r0, r0, r1
172 ; ASM: uxtb r0, r0
173 ; ASM: uxtb r1, r1
174 ; ASM: udiv r0, r0, r1
175 ; ASM: uxtb r0, r0
176 ; ASM: uxtb r1, r1
177 ; ASM: udiv r0, r0, r1
178 ; ASM: uxtb r0, r0
179 ; ASM: uxtb r1, r1
180 ; ASM: udiv r0, r0, r1
181 ; ASM: uxtb r0, r0
182 ; ASM: uxtb r1, r1
183 ; ASM: udiv r0, r0, r1
184 ; ASM: uxtb r0, r0
185 ; ASM: uxtb r1, r1
186 ; ASM: udiv r0, r0, r1
187 ; ASM: uxtb r0, r0
188 ; ASM: uxtb r1, r1
189 ; ASM: udiv r0, r0, r1
190 ; ASM: uxtb r0, r0
191 ; ASM: uxtb r1, r1
192 ; ASM: udiv r0, r0, r1
193 ; ASM: uxtb r0, r0
194 ; ASM: uxtb r1, r1
195 ; ASM: udiv r0, r0, r1
196
197 ; DIS: 214: e6ef0070
198 ; DIS: 218: e6ef1071
199 ; DIS: 21c: e730f110
200 ; DIS: 238: e6ef0070
201 ; DIS: 23c: e6ef1071
202 ; DIS: 240: e730f110
203 ; DIS: 25c: e6ef0070
204 ; DIS: 260: e6ef1071
205 ; DIS: 264: e730f110
206 ; DIS: 280: e6ef0070
207 ; DIS: 284: e6ef1071
208 ; DIS: 288: e730f110
209 ; DIS: 2a4: e6ef0070
210 ; DIS: 2a8: e6ef1071
211 ; DIS: 2ac: e730f110
212 ; DIS: 2c8: e6ef0070
213 ; DIS: 2cc: e6ef1071
214 ; DIS: 2d0: e730f110
215 ; DIS: 2ec: e6ef0070
216 ; DIS: 2f0: e6ef1071
217 ; DIS: 2f4: e730f110
218 ; DIS: 310: e6ef0070
219 ; DIS: 314: e6ef1071
220 ; DIS: 318: e730f110
221 ; DIS: 334: e6ef0070
222 ; DIS: 338: e6ef1071
223 ; DIS: 33c: e730f110
224 ; DIS: 358: e6ef0070
225 ; DIS: 35c: e6ef1071
226 ; DIS: 360: e730f110
227 ; DIS: 37c: e6ef0070
228 ; DIS: 380: e6ef1071
229 ; DIS: 384: e730f110
230 ; DIS: 3a0: e6ef0070
231 ; DIS: 3a4: e6ef1071
232 ; DIS: 3a8: e730f110
233 ; DIS: 3c4: e6ef0070
234 ; DIS: 3c8: e6ef1071
235 ; DIS: 3cc: e730f110
236 ; DIS: 3e8: e6ef0070
237 ; DIS: 3ec: e6ef1071
238 ; DIS: 3f0: e730f110
239 ; DIS: 40c: e6ef0070
240 ; DIS: 410: e6ef1071
241 ; DIS: 414: e730f110
242 ; DIS: 430: e6ef0070
243 ; DIS: 434: e6ef1071
244 ; DIS: 438: e730f110
245
246 ; IASM-NOT: uxtb
247 ; IASM-NOT: udiv
248
249 ret <16 x i8> %res
250 }
OLDNEW
« tests_lit/assembler/arm32/rem-vec.ll ('K') | « tests_lit/assembler/arm32/rem-vec.ll ('k') | tests_lit/assembler/arm32/vabs.ll » ('j') | tests_lit/assembler/arm32/vabs.ll » ('J')

Powered by Google App Engine
This is Rietveld 408576698