ARM32 vector lowering: fabs, scalarize remaining arithmetic operations.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 429 matching lines @@
     return;
   case Inst::Arithmetic: {
     Variable *Dest = Instr->getDest();
     const Type DestTy = Dest->getType();
     const InstArithmetic::OpKind Op =
         llvm::cast<InstArithmetic>(Instr)->getOp();
     if (isVectorType(DestTy)) {
       switch (Op) {
       default:
         break;
+      case InstArithmetic::Ashr:
       case InstArithmetic::Fdiv:
+      case InstArithmetic::Frem:
+      case InstArithmetic::Lshr:
+      case InstArithmetic::Sdiv:
+      case InstArithmetic::Shl:
+      case InstArithmetic::Srem:
       case InstArithmetic::Udiv:
-      case InstArithmetic::Sdiv:
+      case InstArithmetic::Urem:
         scalarizeArithmetic(Op, Dest, Instr->getSrc(0), Instr->getSrc(1));
         Instr->setDeleted();
         return;
       }
     }
     switch (DestTy) {
     default:
       return;
     case IceType_i64: {
       // Technically, ARM has its own aeabi routines, but we can use the
@@ skipping 6331 matching lines @@
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM];
 llvm::SmallBitVector
     TargetARM32::TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM];
 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 
 } // end of namespace ARM32
 } // end of namespace Ice