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Issue 1685253003: ARM32 vector lowering: fabs, scalarize remaining arithmetic operations. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: More lit tests Created 4 years, 10 months ago
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1 ; Show that we know how to translate lsr. 1 ; Show that we know how to translate lsr.
2 2
3 ; NOTE: We use -O2 to get rid of memory stores. 3 ; NOTE: We use -O2 to get rid of memory stores.
4 4
5 ; REQUIRES: allow_dump 5 ; REQUIRES: allow_dump
6 6
7 ; Compile using standalone assembler. 7 ; Compile using standalone assembler.
8 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \ 8 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
9 ; RUN: | FileCheck %s --check-prefix=ASM 9 ; RUN: | FileCheck %s --check-prefix=ASM
10 10
(...skipping 43 matching lines...)
54 54
55 ; ASM-NEXT: lsr r0, r0, r1 55 ; ASM-NEXT: lsr r0, r0, r1
56 ; DIS-NEXT: 10: e1a00130 56 ; DIS-NEXT: 10: e1a00130
57 ; IASM-NEXT: .byte 0x30 57 ; IASM-NEXT: .byte 0x30
58 ; IASM-NEXT: .byte 0x1 58 ; IASM-NEXT: .byte 0x1
59 ; IASM-NEXT: .byte 0xa0 59 ; IASM-NEXT: .byte 0xa0
60 ; IASM-NEXT: .byte 0xe1 60 ; IASM-NEXT: .byte 0xe1
61 61
62 ret i32 %v 62 ret i32 %v
63 } 63 }
64
65 define internal <4 x i32> @LshrVec(<4 x i32> %a, <4 x i32> %b) {
66 ; ASM-LABEL:LshrVec:
67 ; DIS-LABEL:00000020 <LshrVec>:
68 ; IASM-LABEL:LshrVec:
69
70 entry:
71 ; ASM-NEXT:.LLshrVec$entry:
72 ; IASM-NEXT:.LLshrVec$entry:
73
74 %v = lshr <4 x i32> %a, %b
75
76 ; ASM: lsr r0, r0, r1
77 ; ASM: lsr r0, r0, r1
78 ; ASM: lsr r0, r0, r1
79 ; ASM: lsr r0, r0, r1
80 ; DIS: 28: e1a00130
81
82 ret <4 x i32> %v
83 }
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