tests_lit/assembler/arm32/div-vec.ll - Issue 1685253003: ARM32 vector lowering: fabs, scalarize remaining arithmetic operations.

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Issue 1685253003: ARM32 vector lowering: fabs, scalarize remaining arithmetic operations. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master

Patch Set: More lit tests Created 4 years, 10 months ago

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1 ; Show that we know how to translate vector division instructions.	1 ; Show that we know how to translate vector division instructions.

2	2

3 ; REQUIRES: allow_dump	3 ; REQUIRES: allow_dump

4	4

5 ; Compile using standalone assembler.	5 ; Compile using standalone assembler.

6 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 -mattr=hwdiv-arm \	6 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 -mattr=hwdiv-arm \

7 ; RUN: \| FileCheck %s --check-prefix=ASM	7 ; RUN: \| FileCheck %s --check-prefix=ASM

8	8

9 ; Show bytes in assembled standalone code.	9 ; Show bytes in assembled standalone code.

10 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \	10 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \

(...skipping 230 matching lines...) Expand 10 before \| Expand all \| Expand 10 after Loading...
241 ; DIS: 414: e730f110	241 ; DIS: 414: e730f110

242 ; DIS: 430: e6ef0070	242 ; DIS: 430: e6ef0070

243 ; DIS: 434: e6ef1071	243 ; DIS: 434: e6ef1071

244 ; DIS: 438: e730f110	244 ; DIS: 438: e730f110

245	245

246 ; IASM-NOT: uxtb	246 ; IASM-NOT: uxtb

247 ; IASM-NOT: udiv	247 ; IASM-NOT: udiv

248	248

249 ret <16 x i8> %res	249 ret <16 x i8> %res

250 }	250 }

	251

	252 define internal <4 x i32> @testSdiv4i32(<4 x i32> %v1, <4 x i32> %v2) {

	253 ; ASM-LABEL: testSdiv4i32:

	254 ; IASM-LABEL: testSdiv4i32:

	255

	256 entry:

	257 %res = sdiv <4 x i32> %v1, %v2

	258

	259 ; ASM: sdiv r0, r0, r1

	260 ; ASM: sdiv r0, r0, r1

	261 ; ASM: sdiv r0, r0, r1

	262 ; ASM: sdiv r0, r0, r1

	263

	264 ; IASM-NOT: sdiv

	265

	266 ret <4 x i32> %res

	267 }

	268

	269 define internal <8 x i16> @testSdiv8i16(<8 x i16> %v1, <8 x i16> %v2) {

	270 ; ASM-LABEL: testSdiv8i16:

	271 ; IASM-LABEL: testSdiv8i16:

	272

	273 entry:

	274 %res = sdiv <8 x i16> %v1, %v2

	275

	276 ; ASM: sxth r0, r0

	277 ; ASM: sxth r1, r1

	278 ; ASM: sdiv r0, r0, r1

	279 ; ASM: sxth r0, r0

	280 ; ASM: sxth r1, r1

	281 ; ASM: sdiv r0, r0, r1

	282 ; ASM: sxth r0, r0

	283 ; ASM: sxth r1, r1

	284 ; ASM: sdiv r0, r0, r1

	285 ; ASM: sxth r0, r0

	286 ; ASM: sxth r1, r1

	287 ; ASM: sdiv r0, r0, r1

	288 ; ASM: sxth r0, r0

	289 ; ASM: sxth r1, r1

	290 ; ASM: sdiv r0, r0, r1

	291 ; ASM: sxth r0, r0

	292 ; ASM: sxth r1, r1

	293 ; ASM: sdiv r0, r0, r1

	294 ; ASM: sxth r0, r0

	295 ; ASM: sxth r1, r1

	296 ; ASM: sdiv r0, r0, r1

	297 ; ASM: sxth r0, r0

	298 ; ASM: sxth r1, r1

	299 ; ASM: sdiv r0, r0, r1

	300

	301 ; IASM-NOT: sxth

	302 ; IASM-NOT: sdiv

	303

	304 ret <8 x i16> %res

	305 }

	306

	307 define internal <16 x i8> @testSdiv16i8(<16 x i8> %v1, <16 x i8> %v2) {

	308 ; ASM-LABEL: testSdiv16i8:

	309 ; IASM-LABEL: testSdiv16i8:

	310

	311 entry:

	312 %res = sdiv <16 x i8> %v1, %v2

	313

	314 ; ASM: sxtb r0, r0

	315 ; ASM: sxtb r1, r1

	316 ; ASM: sdiv r0, r0, r1

	317 ; ASM: sxtb r0, r0

	318 ; ASM: sxtb r1, r1

	319 ; ASM: sdiv r0, r0, r1

	320 ; ASM: sxtb r0, r0

	321 ; ASM: sxtb r1, r1

	322 ; ASM: sdiv r0, r0, r1

	323 ; ASM: sxtb r0, r0

	324 ; ASM: sxtb r1, r1

	325 ; ASM: sdiv r0, r0, r1

	326 ; ASM: sxtb r0, r0

	327 ; ASM: sxtb r1, r1

	328 ; ASM: sdiv r0, r0, r1

	329 ; ASM: sxtb r0, r0

	330 ; ASM: sxtb r1, r1

	331 ; ASM: sdiv r0, r0, r1

	332 ; ASM: sxtb r0, r0

	333 ; ASM: sxtb r1, r1

	334 ; ASM: sdiv r0, r0, r1

	335 ; ASM: sxtb r0, r0

	336 ; ASM: sxtb r1, r1

	337 ; ASM: sdiv r0, r0, r1

	338 ; ASM: sxtb r0, r0

	339 ; ASM: sxtb r1, r1

	340 ; ASM: sdiv r0, r0, r1

	341 ; ASM: sxtb r0, r0

	342 ; ASM: sxtb r1, r1

	343 ; ASM: sdiv r0, r0, r1

	344 ; ASM: sxtb r0, r0

	345 ; ASM: sxtb r1, r1

	346 ; ASM: sdiv r0, r0, r1

	347 ; ASM: sxtb r0, r0

	348 ; ASM: sxtb r1, r1

	349 ; ASM: sdiv r0, r0, r1

	350 ; ASM: sxtb r0, r0

	351 ; ASM: sxtb r1, r1

	352 ; ASM: sdiv r0, r0, r1

	353 ; ASM: sxtb r0, r0

	354 ; ASM: sxtb r1, r1

	355 ; ASM: sdiv r0, r0, r1

	356 ; ASM: sxtb r0, r0

	357 ; ASM: sxtb r1, r1

	358 ; ASM: sdiv r0, r0, r1

	359 ; ASM: sxtb r0, r0

	360 ; ASM: sxtb r1, r1

	361 ; ASM: sdiv r0, r0, r1

	362

	363 ; IASM-NOT: sxtb

	364 ; IASM-NOT: sdiv

	365

	366 ret <16 x i8> %res

	367 }

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