ARM32 vector lowering: fabs, scalarize remaining arithmetic operations.

tests_lit/assembler/arm32/asr.ll

 ; Show that we know how to translate asr
 
 ; NOTE: We use -O2 to get rid of memory stores.
 
 ; REQUIRES: allow_dump
 
 ; Compile using standalone assembler.
 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
 ; RUN:   | FileCheck %s --check-prefix=ASM
 
@@ skipping 43 matching lines @@
 
 ; ASM-NEXT:     asr     r0, r0, r1
 ; DIS-NEXT:  10:        e1a00150
 ; IASM-NEXT:    .byte 0x50
 ; IASM-NEXT:    .byte 0x1
 ; IASM-NEXT:    .byte 0xa0
 ; IASM-NEXT:    .byte 0xe1
 
   ret i32 %v
 }
+
+define internal <4 x i32> @AshrVec(<4 x i32> %a, <4 x i32> %b) {

[Jim Stichnoth, 2016/02/17 04:15:44]

What about tests for i16 and i8 vectors?

(same for the other vector shift tests)

[Eric Holk, 2016/02/17 19:32:16]

I'll add these.

+; ASM-LABEL:AshrVec:
+; DIS-LABEL:00000020 <AshrVec>:
+; IASM-LABEL:AshrVec:
+
+entry:
+; ASM-NEXT:.LAshrVec$entry:
+; IASM-NEXT:.LAshrVec$entry:
+
+  %v = ashr <4 x i32> %a, %b
+
+; ASM:     asr     r0, r0, r1
+; ASM:     asr     r0, r0, r1
+; ASM:     asr     r0, r0, r1
+; ASM:     asr     r0, r0, r1
+; DIS:  28: e1a00150
+; DIS:  38: e1a00150
+; DIS:  48: e1a00150
+; DIS:  58: e1a00150
+
+  ret <4 x i32> %v
+}