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Side by Side Diff: src/IceTargetLoweringARM32.cpp

Issue 1685253003: ARM32 vector lowering: fabs, scalarize remaining arithmetic operations. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: More lit tests Created 4 years, 10 months ago
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1 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===// 1 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 /// 9 ///
10 /// \file 10 /// \file
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439 return; 439 return;
440 case Inst::Arithmetic: { 440 case Inst::Arithmetic: {
441 Variable *Dest = Instr->getDest(); 441 Variable *Dest = Instr->getDest();
442 const Type DestTy = Dest->getType(); 442 const Type DestTy = Dest->getType();
443 const InstArithmetic::OpKind Op = 443 const InstArithmetic::OpKind Op =
444 llvm::cast<InstArithmetic>(Instr)->getOp(); 444 llvm::cast<InstArithmetic>(Instr)->getOp();
445 if (isVectorType(DestTy)) { 445 if (isVectorType(DestTy)) {
446 switch (Op) { 446 switch (Op) {
447 default: 447 default:
448 break; 448 break;
449 case InstArithmetic::Ashr:
449 case InstArithmetic::Fdiv: 450 case InstArithmetic::Fdiv:
451 case InstArithmetic::Frem:
452 case InstArithmetic::Lshr:
453 case InstArithmetic::Sdiv:
454 case InstArithmetic::Shl:
455 case InstArithmetic::Srem:
450 case InstArithmetic::Udiv: 456 case InstArithmetic::Udiv:
451 case InstArithmetic::Sdiv: 457 case InstArithmetic::Urem:
452 scalarizeArithmetic(Op, Dest, Instr->getSrc(0), Instr->getSrc(1)); 458 scalarizeArithmetic(Op, Dest, Instr->getSrc(0), Instr->getSrc(1));
453 Instr->setDeleted(); 459 Instr->setDeleted();
454 return; 460 return;
455 } 461 }
456 } 462 }
457 switch (DestTy) { 463 switch (DestTy) {
458 default: 464 default:
459 return; 465 return;
460 case IceType_i64: { 466 case IceType_i64: {
461 // Technically, ARM has its own aeabi routines, but we can use the 467 // Technically, ARM has its own aeabi routines, but we can use the
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5029 Variable *T = makeReg(IceType_i32); 5035 Variable *T = makeReg(IceType_i32);
5030 _rbit(T, ValLoR); 5036 _rbit(T, ValLoR);
5031 ValLoR = T; 5037 ValLoR = T;
5032 } 5038 }
5033 lowerCLZ(Dest, ValLoR, ValHiR); 5039 lowerCLZ(Dest, ValLoR, ValHiR);
5034 return; 5040 return;
5035 } 5041 }
5036 case Intrinsics::Fabs: { 5042 case Intrinsics::Fabs: {
5037 Type DestTy = Dest->getType(); 5043 Type DestTy = Dest->getType();
5038 Variable *T = makeReg(DestTy); 5044 Variable *T = makeReg(DestTy);
5039 if (isVectorType(DestTy)) {
5040 UnimplementedLoweringError(this, Instr);
5041 return;
5042 }
5043 _vabs(T, legalizeToReg(Instr->getArg(0))); 5045 _vabs(T, legalizeToReg(Instr->getArg(0)));
5044 _mov(Dest, T); 5046 _mov(Dest, T);
5045 return; 5047 return;
5046 } 5048 }
5047 case Intrinsics::Longjmp: { 5049 case Intrinsics::Longjmp: {
5048 llvm::report_fatal_error("longjmp should have been prelowered."); 5050 llvm::report_fatal_error("longjmp should have been prelowered.");
5049 } 5051 }
5050 case Intrinsics::Memcpy: { 5052 case Intrinsics::Memcpy: {
5051 llvm::report_fatal_error("memcpy should have been prelowered."); 5053 llvm::report_fatal_error("memcpy should have been prelowered.");
5052 } 5054 }
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6870 Str << ".eabi_attribute 14, 3 @ Tag_ABI_PCS_R9_use: Not used\n"; 6872 Str << ".eabi_attribute 14, 3 @ Tag_ABI_PCS_R9_use: Not used\n";
6871 } 6873 }
6872 6874
6873 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM]; 6875 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM];
6874 llvm::SmallBitVector 6876 llvm::SmallBitVector
6875 TargetARM32::TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM]; 6877 TargetARM32::TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM];
6876 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM]; 6878 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
6877 6879
6878 } // end of namespace ARM32 6880 } // end of namespace ARM32
6879 } // end of namespace Ice 6881 } // end of namespace Ice
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