libvpx: Pull from upstream

source/libvpx/vp9/common/mips/dspr2/vp9_itrans32_dspr2.c

 /*
  *  Copyright (c) 2013 The WebM project authors. All Rights Reserved.
  *
  *  Use of this source code is governed by a BSD-style license
  *  that can be found in the LICENSE file in the root of the source
  *  tree. An additional intellectual property rights grant can be found
  *  in the file PATENTS.  All contributing project authors may
  *  be found in the AUTHORS file in the root of the source tree.
  */
 
 #include <assert.h>
 #include <stdio.h>
 
 #include "./vpx_config.h"
 #include "./vp9_rtcd.h"
 #include "vp9/common/vp9_common.h"
 #include "vp9/common/vp9_blockd.h"
 #include "vp9/common/vp9_idct.h"
 #include "vp9/common/mips/dspr2/vp9_common_dspr2.h"
 
 #if HAVE_DSPR2
-static void idct32_1d_rows_dspr2(const int16_t *input, int16_t *output,
-                                 uint32_t no_rows) {
+static void idct32_rows_dspr2(const int16_t *input, int16_t *output,
+                              uint32_t no_rows) {
   int16_t step1_0, step1_1, step1_2, step1_3, step1_4, step1_5, step1_6;
   int16_t step1_7, step1_8, step1_9, step1_10, step1_11, step1_12, step1_13;
   int16_t step1_14, step1_15, step1_16, step1_17, step1_18, step1_19, step1_20;
   int16_t step1_21, step1_22, step1_23, step1_24, step1_25, step1_26, step1_27;
   int16_t step1_28, step1_29, step1_30, step1_31;
   int16_t step2_0, step2_1, step2_2, step2_3, step2_4, step2_5, step2_6;
   int16_t step2_7, step2_8, step2_9, step2_10, step2_11, step2_12, step2_13;
   int16_t step2_14, step2_15, step2_16, step2_17, step2_18, step2_19, step2_20;
   int16_t step2_21, step2_22, step2_23, step2_24, step2_25, step2_26, step2_27;
   int16_t step2_28, step2_29, step2_30, step2_31;
@@ skipping 841 matching lines @@
   uint32_t pos = 45;
 
   /* bit positon for extract from acc */
   __asm__ __volatile__ (
     "wrdsp      %[pos],     1           \n\t"
     :
     : [pos] "r" (pos)
   );
 
   // Rows
-  idct32_1d_rows_dspr2(input, outptr, 32);
+  idct32_rows_dspr2(input, outptr, 32);
 
   // Columns
-  vp9_idct32_1d_cols_add_blk_dspr2(out, dest, dest_stride);
+  vp9_idct32_cols_add_blk_dspr2(out, dest, dest_stride);
 }
 
 void vp9_idct32x32_34_add_dspr2(const int16_t *input, uint8_t *dest,
                                 int stride) {
   DECLARE_ALIGNED(32, int16_t,  out[32 * 32]);
   int16_t *outptr = out;
   uint32_t i;
   uint32_t pos = 45;
 
   /* bit positon for extract from acc */
   __asm__ __volatile__ (
     "wrdsp      %[pos],     1           \n\t"
     :
     : [pos] "r" (pos)
   );
 
   // Rows
-  idct32_1d_rows_dspr2(input, outptr, 8);
+  idct32_rows_dspr2(input, outptr, 8);
 
   outptr += 8;
   __asm__ __volatile__ (
       "sw     $zero,      0(%[outptr])     \n\t"
       "sw     $zero,      4(%[outptr])     \n\t"
       "sw     $zero,      8(%[outptr])     \n\t"
       "sw     $zero,     12(%[outptr])     \n\t"
       "sw     $zero,     16(%[outptr])     \n\t"
       "sw     $zero,     20(%[outptr])     \n\t"
       "sw     $zero,     24(%[outptr])     \n\t"
@@ skipping 23 matching lines @@
         "sw     $zero,     36(%[outptr])     \n\t"
         "sw     $zero,     40(%[outptr])     \n\t"
         "sw     $zero,     44(%[outptr])     \n\t"
 
         :
         : [outptr] "r" (outptr)
     );
   }
 
   // Columns
-  vp9_idct32_1d_cols_add_blk_dspr2(out, dest, stride);
+  vp9_idct32_cols_add_blk_dspr2(out, dest, stride);
 }
 
 void vp9_idct32x32_1_add_dspr2(const int16_t *input, uint8_t *dest,
                                int stride) {
   int       r, out;
   int32_t   a1, absa1;
   int32_t   vector_a1;
   int32_t   t1, t2, t3, t4;
   int32_t   vector_1, vector_2, vector_3, vector_4;
   uint32_t  pos = 45;
@@ skipping 106 matching lines @@
           : [t1] "=&r" (t1), [t2] "=&r" (t2), [t3] "=&r" (t3), [t4] "=&r" (t4),
             [vector_1] "=&r" (vector_1), [vector_2] "=&r" (vector_2),
             [vector_3] "=&r" (vector_3), [vector_4] "=&r" (vector_4),
             [dest] "+&r" (dest)
           : [stride] "r" (stride), [vector_a1] "r" (vector_a1)
       );
     }
   }
 }
 #endif  // #if HAVE_DSPR2