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Issue 1683243003: ARM32 Vector lowering - scalarize select (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Typo fix Created 4 years, 10 months ago
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1 ; Test that we handle select on vectors.
2
3 ; TODO(eholk): This test will need to be updated once comparison is no longer
4 ; scalarized.
5
6 ; REQUIRES: allow_dump
7
8 ; Compile using standalone assembler.
9 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
10 ; RUN: | FileCheck %s --check-prefix=ASM
11
12 define internal <4 x float> @select4float(<4 x i1> %s, <4 x float> %a,
13 <4 x float> %b) {
14 ; ASM-LABEL:select4float:
15 ; DIS-LABEL:00000000 <select4float>:
16
17 entry:
18 %res = select <4 x i1> %s, <4 x float> %a, <4 x float> %b
19
20 ; ASM: # q3 = def.pseudo
21 ; ASM-NEXT: vmov.s8 r0, d0[0]
22 ; ASM-NEXT: vmov.f32 s16, s4
23 ; ASM-NEXT: vmov.f32 s17, s8
24 ; ASM-NEXT: tst r0, #1
25 ; ASM-NEXT: vmovne.f32 s17, s16
26 ; ASM-NEXT: vmov.f32 s12, s17
27 ; ASM-NEXT: vmov.s8 r0, d0[1]
28 ; ASM-NEXT: vmov.f32 s16, s5
29 ; ASM-NEXT: vmov.f32 s17, s9
30 ; ASM-NEXT: tst r0, #1
31 ; ASM-NEXT: vmovne.f32 s17, s16
32 ; ASM-NEXT: vmov.f32 s13, s17
33 ; ASM-NEXT: vmov.s8 r0, d1[0]
34 ; ASM-NEXT: vmov.f32 s16, s6
35 ; ASM-NEXT: vmov.f32 s17, s10
36 ; ASM-NEXT: tst r0, #1
37 ; ASM-NEXT: vmovne.f32 s17, s16
38 ; ASM-NEXT: vmov.f32 s14, s17
39 ; ASM-NEXT: vmov.s8 r0, d1[1]
40 ; ASM-NEXT: vmov.f32 s4, s7
41 ; ASM-NEXT: vmov.f32 s8, s11
42 ; ASM-NEXT: tst r0, #1
43 ; ASM-NEXT: vmovne.f32 s8, s4
44 ; ASM-NEXT: vmov.f32 s15, s8
45 ; ASM-NEXT: vmov.f32 q0, q3
46 ; ASM-NEXT: vpop {s16, s17}
47 ; ASM-NEXT: # s16 = def.pseudo
48 ; ASM-NEXT: # s17 = def.pseudo
49 ; ASM-NEXT: bx lr
50
51 ret <4 x float> %res
52 }
53
54 define internal <4 x i32> @select4i32(<4 x i1> %s, <4 x i32> %a, <4 x i32> %b) {
55 ; ASM-LABEL:select4i32:
56 ; DIS-LABEL:00000000 <select4i32>:
57
58 entry:
59 %res = select <4 x i1> %s, <4 x i32> %a, <4 x i32> %b
60
61 ; ASM: # q3 = def.pseudo
62 ; ASM-NEXT: vmov.s8 r0, d0[0]
63 ; ASM-NEXT: vmov.32 r1, d2[0]
64 ; ASM-NEXT: vmov.32 r2, d4[0]
65 ; ASM-NEXT: tst r0, #1
66 ; ASM-NEXT: movne r2, r1
67 ; ASM-NEXT: vmov.32 d6[0], r2
68 ; ASM-NEXT: vmov.s8 r0, d0[1]
69 ; ASM-NEXT: vmov.32 r1, d2[1]
70 ; ASM-NEXT: vmov.32 r2, d4[1]
71 ; ASM-NEXT: tst r0, #1
72 ; ASM-NEXT: movne r2, r1
73 ; ASM-NEXT: vmov.32 d6[1], r2
74 ; ASM-NEXT: vmov.s8 r0, d1[0]
75 ; ASM-NEXT: vmov.32 r1, d3[0]
76 ; ASM-NEXT: vmov.32 r2, d5[0]
77 ; ASM-NEXT: tst r0, #1
78 ; ASM-NEXT: movne r2, r1
79 ; ASM-NEXT: vmov.32 d7[0], r2
80 ; ASM-NEXT: vmov.s8 r0, d1[1]
81 ; ASM-NEXT: vmov.32 r1, d3[1]
82 ; ASM-NEXT: vmov.32 r2, d5[1]
83 ; ASM-NEXT: tst r0, #1
84 ; ASM-NEXT: movne r2, r1
85 ; ASM-NEXT: vmov.32 d7[1], r2
86 ; ASM-NEXT: vmov.i32 q0, q3
87 ; ASM-NEXT: bx lr
88
89 ret <4 x i32> %res
90 }
91
92 define internal <8 x i16> @select8i16(<8 x i1> %s, <8 x i16> %a, <8 x i16> %b) {
93 ; ASM-LABEL:select8i16:
94 ; DIS-LABEL:00000000 <select8i16>:
95
96 entry:
97 %res = select <8 x i1> %s, <8 x i16> %a, <8 x i16> %b
98
99 ; ASM: # q3 = def.pseudo
100 ; ASM-NEXT: vmov.s8 r0, d0[0]
101 ; ASM-NEXT: vmov.s16 r1, d2[0]
102 ; ASM-NEXT: vmov.s16 r2, d4[0]
103 ; ASM-NEXT: tst r0, #1
104 ; ASM-NEXT: movne r2, r1
105 ; ASM-NEXT: vmov.16 d6[0], r2
106 ; ASM-NEXT: vmov.s8 r0, d0[1]
107 ; ASM-NEXT: vmov.s16 r1, d2[1]
108 ; ASM-NEXT: vmov.s16 r2, d4[1]
109 ; ASM-NEXT: tst r0, #1
110 ; ASM-NEXT: movne r2, r1
111 ; ASM-NEXT: vmov.16 d6[1], r2
112 ; ASM-NEXT: vmov.s8 r0, d0[2]
113 ; ASM-NEXT: vmov.s16 r1, d2[2]
114 ; ASM-NEXT: vmov.s16 r2, d4[2]
115 ; ASM-NEXT: tst r0, #1
116 ; ASM-NEXT: movne r2, r1
117 ; ASM-NEXT: vmov.16 d6[2], r2
118 ; ASM-NEXT: vmov.s8 r0, d0[3]
119 ; ASM-NEXT: vmov.s16 r1, d2[3]
120 ; ASM-NEXT: vmov.s16 r2, d4[3]
121 ; ASM-NEXT: tst r0, #1
122 ; ASM-NEXT: movne r2, r1
123 ; ASM-NEXT: vmov.16 d6[3], r2
124 ; ASM-NEXT: vmov.s8 r0, d1[0]
125 ; ASM-NEXT: vmov.s16 r1, d3[0]
126 ; ASM-NEXT: vmov.s16 r2, d5[0]
127 ; ASM-NEXT: tst r0, #1
128 ; ASM-NEXT: movne r2, r1
129 ; ASM-NEXT: vmov.16 d7[0], r2
130 ; ASM-NEXT: vmov.s8 r0, d1[1]
131 ; ASM-NEXT: vmov.s16 r1, d3[1]
132 ; ASM-NEXT: vmov.s16 r2, d5[1]
133 ; ASM-NEXT: tst r0, #1
134 ; ASM-NEXT: movne r2, r1
135 ; ASM-NEXT: vmov.16 d7[1], r2
136 ; ASM-NEXT: vmov.s8 r0, d1[2]
137 ; ASM-NEXT: vmov.s16 r1, d3[2]
138 ; ASM-NEXT: vmov.s16 r2, d5[2]
139 ; ASM-NEXT: tst r0, #1
140 ; ASM-NEXT: movne r2, r1
141 ; ASM-NEXT: vmov.16 d7[2], r2
142 ; ASM-NEXT: vmov.s8 r0, d1[3]
143 ; ASM-NEXT: vmov.s16 r1, d3[3]
144 ; ASM-NEXT: vmov.s16 r2, d5[3]
145 ; ASM-NEXT: tst r0, #1
146 ; ASM-NEXT: movne r2, r1
147 ; ASM-NEXT: vmov.16 d7[3], r2
148 ; ASM-NEXT: vmov.i16 q0, q3
149 ; ASM-NEXT: bx lr
150
151 ret <8 x i16> %res
152 }
153
154 define internal <16 x i8> @select16i8(<16 x i1> %s, <16 x i8> %a,
155 <16 x i8> %b) {
156 ; ASM-LABEL:select16i8:
157 ; DIS-LABEL:00000000 <select16i8>:
158
159 entry:
160 %res = select <16 x i1> %s, <16 x i8> %a, <16 x i8> %b
161
162 ; ASM: # q3 = def.pseudo
163 ; ASM-NEXT: vmov.s8 r0, d0[0]
164 ; ASM-NEXT: vmov.s8 r1, d2[0]
165 ; ASM-NEXT: vmov.s8 r2, d4[0]
166 ; ASM-NEXT: tst r0, #1
167 ; ASM-NEXT: movne r2, r1
168 ; ASM-NEXT: vmov.8 d6[0], r2
169 ; ASM-NEXT: vmov.s8 r0, d0[1]
170 ; ASM-NEXT: vmov.s8 r1, d2[1]
171 ; ASM-NEXT: vmov.s8 r2, d4[1]
172 ; ASM-NEXT: tst r0, #1
173 ; ASM-NEXT: movne r2, r1
174 ; ASM-NEXT: vmov.8 d6[1], r2
175 ; ASM-NEXT: vmov.s8 r0, d0[2]
176 ; ASM-NEXT: vmov.s8 r1, d2[2]
177 ; ASM-NEXT: vmov.s8 r2, d4[2]
178 ; ASM-NEXT: tst r0, #1
179 ; ASM-NEXT: movne r2, r1
180 ; ASM-NEXT: vmov.8 d6[2], r2
181 ; ASM-NEXT: vmov.s8 r0, d0[3]
182 ; ASM-NEXT: vmov.s8 r1, d2[3]
183 ; ASM-NEXT: vmov.s8 r2, d4[3]
184 ; ASM-NEXT: tst r0, #1
185 ; ASM-NEXT: movne r2, r1
186 ; ASM-NEXT: vmov.8 d6[3], r2
187 ; ASM-NEXT: vmov.s8 r0, d0[4]
188 ; ASM-NEXT: vmov.s8 r1, d2[4]
189 ; ASM-NEXT: vmov.s8 r2, d4[4]
190 ; ASM-NEXT: tst r0, #1
191 ; ASM-NEXT: movne r2, r1
192 ; ASM-NEXT: vmov.8 d6[4], r2
193 ; ASM-NEXT: vmov.s8 r0, d0[5]
194 ; ASM-NEXT: vmov.s8 r1, d2[5]
195 ; ASM-NEXT: vmov.s8 r2, d4[5]
196 ; ASM-NEXT: tst r0, #1
197 ; ASM-NEXT: movne r2, r1
198 ; ASM-NEXT: vmov.8 d6[5], r2
199 ; ASM-NEXT: vmov.s8 r0, d0[6]
200 ; ASM-NEXT: vmov.s8 r1, d2[6]
201 ; ASM-NEXT: vmov.s8 r2, d4[6]
202 ; ASM-NEXT: tst r0, #1
203 ; ASM-NEXT: movne r2, r1
204 ; ASM-NEXT: vmov.8 d6[6], r2
205 ; ASM-NEXT: vmov.s8 r0, d0[7]
206 ; ASM-NEXT: vmov.s8 r1, d2[7]
207 ; ASM-NEXT: vmov.s8 r2, d4[7]
208 ; ASM-NEXT: tst r0, #1
209 ; ASM-NEXT: movne r2, r1
210 ; ASM-NEXT: vmov.8 d6[7], r2
211 ; ASM-NEXT: vmov.s8 r0, d1[0]
212 ; ASM-NEXT: vmov.s8 r1, d3[0]
213 ; ASM-NEXT: vmov.s8 r2, d5[0]
214 ; ASM-NEXT: tst r0, #1
215 ; ASM-NEXT: movne r2, r1
216 ; ASM-NEXT: vmov.8 d7[0], r2
217 ; ASM-NEXT: vmov.s8 r0, d1[1]
218 ; ASM-NEXT: vmov.s8 r1, d3[1]
219 ; ASM-NEXT: vmov.s8 r2, d5[1]
220 ; ASM-NEXT: tst r0, #1
221 ; ASM-NEXT: movne r2, r1
222 ; ASM-NEXT: vmov.8 d7[1], r2
223 ; ASM-NEXT: vmov.s8 r0, d1[2]
224 ; ASM-NEXT: vmov.s8 r1, d3[2]
225 ; ASM-NEXT: vmov.s8 r2, d5[2]
226 ; ASM-NEXT: tst r0, #1
227 ; ASM-NEXT: movne r2, r1
228 ; ASM-NEXT: vmov.8 d7[2], r2
229 ; ASM-NEXT: vmov.s8 r0, d1[3]
230 ; ASM-NEXT: vmov.s8 r1, d3[3]
231 ; ASM-NEXT: vmov.s8 r2, d5[3]
232 ; ASM-NEXT: tst r0, #1
233 ; ASM-NEXT: movne r2, r1
234 ; ASM-NEXT: vmov.8 d7[3], r2
235 ; ASM-NEXT: vmov.s8 r0, d1[4]
236 ; ASM-NEXT: vmov.s8 r1, d3[4]
237 ; ASM-NEXT: vmov.s8 r2, d5[4]
238 ; ASM-NEXT: tst r0, #1
239 ; ASM-NEXT: movne r2, r1
240 ; ASM-NEXT: vmov.8 d7[4], r2
241 ; ASM-NEXT: vmov.s8 r0, d1[5]
242 ; ASM-NEXT: vmov.s8 r1, d3[5]
243 ; ASM-NEXT: vmov.s8 r2, d5[5]
244 ; ASM-NEXT: tst r0, #1
245 ; ASM-NEXT: movne r2, r1
246 ; ASM-NEXT: vmov.8 d7[5], r2
247 ; ASM-NEXT: vmov.s8 r0, d1[6]
248 ; ASM-NEXT: vmov.s8 r1, d3[6]
249 ; ASM-NEXT: vmov.s8 r2, d5[6]
250 ; ASM-NEXT: tst r0, #1
251 ; ASM-NEXT: movne r2, r1
252 ; ASM-NEXT: vmov.8 d7[6], r2
253 ; ASM-NEXT: vmov.s8 r0, d1[7]
254 ; ASM-NEXT: vmov.s8 r1, d3[7]
255 ; ASM-NEXT: vmov.s8 r2, d5[7]
256 ; ASM-NEXT: tst r0, #1
257 ; ASM-NEXT: movne r2, r1
258 ; ASM-NEXT: vmov.8 d7[7], r2
259 ; ASM-NEXT: vmov.i8 q0, q3
260 ; ASM-NEXT: bx lr
261
262 ret <16 x i8> %res
263 }
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