OLD | NEW |
1 ; Show that we know how to translate vector division instructions. | 1 ; Show that we know how to translate vector division instructions. |
2 | 2 |
3 ; REQUIRES: allow_dump | 3 ; REQUIRES: allow_dump |
4 | 4 |
5 ; Compile using standalone assembler. | 5 ; Compile using standalone assembler. |
6 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 -mattr=hwdiv-arm \ | 6 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 -mattr=hwdiv-arm \ |
7 ; RUN: | FileCheck %s --check-prefix=ASM | 7 ; RUN: | FileCheck %s --check-prefix=ASM |
8 | 8 |
9 ; Show bytes in assembled standalone code. | 9 ; Show bytes in assembled standalone code. |
10 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \ | 10 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \ |
(...skipping 13 matching lines...) Expand all Loading... |
24 ; ASM-LABEL: testVdivFloat4: | 24 ; ASM-LABEL: testVdivFloat4: |
25 ; DIS-LABEL: 00000000 <testVdivFloat4>: | 25 ; DIS-LABEL: 00000000 <testVdivFloat4>: |
26 ; IASM-LABEL: testVdivFloat4: | 26 ; IASM-LABEL: testVdivFloat4: |
27 | 27 |
28 entry: | 28 entry: |
29 %res = fdiv <4 x float> %v1, %v2 | 29 %res = fdiv <4 x float> %v1, %v2 |
30 | 30 |
31 ; TODO(eholk): this code could be a lot better. Fix the code generator | 31 ; TODO(eholk): this code could be a lot better. Fix the code generator |
32 ; and update the test. Same for the rest of the tests. | 32 ; and update the test. Same for the rest of the tests. |
33 | 33 |
34 ; ASM: vdiv.f32 s8, s8, s9 | 34 ; ASM: vdiv.f32 s12, s12, s13 |
35 ; ASM: vdiv.f32 s8, s8, s9 | 35 ; ASM-NEXT: vmov.f32» s8, s12 |
36 ; ASM: vdiv.f32 s8, s8, s9 | 36 ; ASM: vdiv.f32 s12, s12, s13 |
37 ; ASM: vdiv.f32 s0, s0, s4 | 37 ; ASM-NEXT: vmov.f32» s9, s12 |
| 38 ; ASM: vdiv.f32 s12, s12, s13 |
| 39 ; ASM-NEXT: vmov.f32» s10, s12 |
| 40 ; ASM: vdiv.f32 s0, s0, s4 |
| 41 ; ASM-NEXT: vmov.f32» s11, s0 |
38 | 42 |
39 ; DIS: 8:» ee844a24 | 43 ; DIS: 8:» ee866a26 |
40 ; DIS: 1c:» ee844a24 | 44 ; DIS: 18:» ee866a26 |
41 ; DIS: 2c:» ee844a24 | 45 ; DIS: 28:» ee866a26 |
42 ; DIS: 3c:» ee800a02 | 46 ; DIS: 38:» ee800a02 |
43 | 47 |
44 ; IASM-NOT: vdiv | 48 ; IASM-NOT: vdiv |
45 | 49 |
46 ret <4 x float> %res | 50 ret <4 x float> %res |
47 } | 51 } |
48 | 52 |
49 define internal <4 x i32> @testVdiv4i32(<4 x i32> %v1, <4 x i32> %v2) { | 53 define internal <4 x i32> @testVdiv4i32(<4 x i32> %v1, <4 x i32> %v2) { |
50 ; ASM-LABEL: testVdiv4i32: | 54 ; ASM-LABEL: testVdiv4i32: |
51 ; DIS-LABEL: 00000050 <testVdiv4i32>: | 55 ; DIS-LABEL: 00000050 <testVdiv4i32>: |
52 ; IASM-LABEL: testVdiv4i32: | 56 ; IASM-LABEL: testVdiv4i32: |
53 | 57 |
54 entry: | 58 entry: |
55 %res = udiv <4 x i32> %v1, %v2 | 59 %res = udiv <4 x i32> %v1, %v2 |
56 | 60 |
57 ; ASM: udiv r0, r0, r1 | 61 ; ASM: udiv r0, r0, r1 |
58 ; ASM: udiv r0, r0, r1 | 62 ; ASM: udiv r0, r0, r1 |
59 ; ASM: udiv r0, r0, r1 | 63 ; ASM: udiv r0, r0, r1 |
60 ; ASM: udiv r0, r0, r1 | 64 ; ASM: udiv r0, r0, r1 |
61 | 65 |
62 ; DIS: 64: e730f110 | 66 ; DIS: 64: e730f110 |
63 ; DIS: 84:» e730f110 | 67 ; DIS: 80:» e730f110 |
64 ; DIS: a0:» e730f110 | 68 ; DIS: 9c:» e730f110 |
65 ; DIS: bc:» e730f110 | 69 ; DIS: b8:» e730f110 |
66 | 70 |
67 ; IASM-NOT: udiv | 71 ; IASM-NOT: udiv |
68 | 72 |
69 ret <4 x i32> %res | 73 ret <4 x i32> %res |
70 } | 74 } |
71 | 75 |
72 define internal <8 x i16> @testVdiv8i16(<8 x i16> %v1, <8 x i16> %v2) { | 76 define internal <8 x i16> @testVdiv8i16(<8 x i16> %v1, <8 x i16> %v2) { |
73 ; ASM-LABEL: testVdiv8i16: | 77 ; ASM-LABEL: testVdiv8i16: |
74 ; DIS-LABEL: 000000d0 <testVdiv8i16>: | 78 ; DIS-LABEL: 000000d0 <testVdiv8i16>: |
75 ; IASM-LABEL: testVdiv8i16: | 79 ; IASM-LABEL: testVdiv8i16: |
(...skipping 22 matching lines...) Expand all Loading... |
98 ; ASM: uxth r0, r0 | 102 ; ASM: uxth r0, r0 |
99 ; ASM: uxth r1, r1 | 103 ; ASM: uxth r1, r1 |
100 ; ASM: udiv r0, r0, r1 | 104 ; ASM: udiv r0, r0, r1 |
101 ; ASM: uxth r0, r0 | 105 ; ASM: uxth r0, r0 |
102 ; ASM: uxth r1, r1 | 106 ; ASM: uxth r1, r1 |
103 ; ASM: udiv r0, r0, r1 | 107 ; ASM: udiv r0, r0, r1 |
104 | 108 |
105 ; DIS: e4: e6ff0070 | 109 ; DIS: e4: e6ff0070 |
106 ; DIS: e8: e6ff1071 | 110 ; DIS: e8: e6ff1071 |
107 ; DIS: ec: e730f110 | 111 ; DIS: ec: e730f110 |
108 ; DIS: 10c:» e6ff0070 | 112 ; DIS: 108:» e6ff0070 |
109 ; DIS: 110:» e6ff1071 | 113 ; DIS: 10c:» e6ff1071 |
110 ; DIS: 114:» e730f110 | 114 ; DIS: 110:» e730f110 |
111 ; DIS: 130:» e6ff0070 | 115 ; DIS: 12c:» e6ff0070 |
112 ; DIS: 134:» e6ff1071 | 116 ; DIS: 130:» e6ff1071 |
113 ; DIS: 138:» e730f110 | 117 ; DIS: 134:» e730f110 |
114 ; DIS: 154:» e6ff0070 | 118 ; DIS: 150:» e6ff0070 |
115 ; DIS: 158:» e6ff1071 | 119 ; DIS: 154:» e6ff1071 |
116 ; DIS: 15c:» e730f110 | 120 ; DIS: 158:» e730f110 |
117 ; DIS: 178:» e6ff0070 | 121 ; DIS: 174:» e6ff0070 |
118 ; DIS: 17c:» e6ff1071 | 122 ; DIS: 178:» e6ff1071 |
119 ; DIS: 180:» e730f110 | 123 ; DIS: 17c:» e730f110 |
120 ; DIS: 19c:» e6ff0070 | 124 ; DIS: 198:» e6ff0070 |
121 ; DIS: 1a0:» e6ff1071 | 125 ; DIS: 19c:» e6ff1071 |
122 ; DIS: 1a4:» e730f110 | 126 ; DIS: 1a0:» e730f110 |
123 ; DIS: 1c0:» e6ff0070 | 127 ; DIS: 1bc:» e6ff0070 |
124 ; DIS: 1c4:» e6ff1071 | 128 ; DIS: 1c0:» e6ff1071 |
125 ; DIS: 1c8:» e730f110 | 129 ; DIS: 1c4:» e730f110 |
126 ; DIS: 1e4:» e6ff0070 | 130 ; DIS: 1e0:» e6ff0070 |
127 ; DIS: 1e8:» e6ff1071 | 131 ; DIS: 1e4:» e6ff1071 |
128 ; DIS: 1ec:» e730f110 | 132 ; DIS: 1e8:» e730f110 |
129 | 133 |
130 ; IASM-NOT: uxth | 134 ; IASM-NOT: uxth |
131 ; IASM-NOT: udiv | 135 ; IASM-NOT: udiv |
132 | 136 |
133 ret <8 x i16> %res | 137 ret <8 x i16> %res |
134 } | 138 } |
135 | 139 |
136 define internal <16 x i8> @testVdiv16i8(<16 x i8> %v1, <16 x i8> %v2) { | 140 define internal <16 x i8> @testVdiv16i8(<16 x i8> %v1, <16 x i8> %v2) { |
137 ; ASM-LABEL: testVdiv16i8: | 141 ; ASM-LABEL: testVdiv16i8: |
138 ; DIS-LABEL: 00000200 <testVdiv16i8>: | 142 ; DIS-LABEL: 00000200 <testVdiv16i8>: |
(...skipping 47 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
186 ; ASM: uxtb r0, r0 | 190 ; ASM: uxtb r0, r0 |
187 ; ASM: uxtb r1, r1 | 191 ; ASM: uxtb r1, r1 |
188 ; ASM: udiv r0, r0, r1 | 192 ; ASM: udiv r0, r0, r1 |
189 ; ASM: uxtb r0, r0 | 193 ; ASM: uxtb r0, r0 |
190 ; ASM: uxtb r1, r1 | 194 ; ASM: uxtb r1, r1 |
191 ; ASM: udiv r0, r0, r1 | 195 ; ASM: udiv r0, r0, r1 |
192 | 196 |
193 ; DIS: 214: e6ef0070 | 197 ; DIS: 214: e6ef0070 |
194 ; DIS: 218: e6ef1071 | 198 ; DIS: 218: e6ef1071 |
195 ; DIS: 21c: e730f110 | 199 ; DIS: 21c: e730f110 |
196 ; DIS: 23c:» e6ef0070 | 200 ; DIS: 238:» e6ef0070 |
197 ; DIS: 240:» e6ef1071 | 201 ; DIS: 23c:» e6ef1071 |
198 ; DIS: 244:» e730f110 | 202 ; DIS: 240:» e730f110 |
199 ; DIS: 260:» e6ef0070 | 203 ; DIS: 25c:» e6ef0070 |
200 ; DIS: 264:» e6ef1071 | 204 ; DIS: 260:» e6ef1071 |
201 ; DIS: 268:» e730f110 | 205 ; DIS: 264:» e730f110 |
202 ; DIS: 284:» e6ef0070 | 206 ; DIS: 280:» e6ef0070 |
203 ; DIS: 288:» e6ef1071 | 207 ; DIS: 284:» e6ef1071 |
204 ; DIS: 28c:» e730f110 | 208 ; DIS: 288:» e730f110 |
205 ; DIS: 2a8:» e6ef0070 | 209 ; DIS: 2a4:» e6ef0070 |
206 ; DIS: 2ac:» e6ef1071 | 210 ; DIS: 2a8:» e6ef1071 |
207 ; DIS: 2b0:» e730f110 | 211 ; DIS: 2ac:» e730f110 |
208 ; DIS: 2cc:» e6ef0070 | 212 ; DIS: 2c8:» e6ef0070 |
209 ; DIS: 2d0:» e6ef1071 | 213 ; DIS: 2cc:» e6ef1071 |
210 ; DIS: 2d4:» e730f110 | 214 ; DIS: 2d0:» e730f110 |
211 ; DIS: 2f0:» e6ef0070 | 215 ; DIS: 2ec:» e6ef0070 |
212 ; DIS: 2f4:» e6ef1071 | 216 ; DIS: 2f0:» e6ef1071 |
213 ; DIS: 2f8:» e730f110 | 217 ; DIS: 2f4:» e730f110 |
214 ; DIS: 314:» e6ef0070 | 218 ; DIS: 310:» e6ef0070 |
215 ; DIS: 318:» e6ef1071 | 219 ; DIS: 314:» e6ef1071 |
216 ; DIS: 31c:» e730f110 | 220 ; DIS: 318:» e730f110 |
217 ; DIS: 338:» e6ef0070 | 221 ; DIS: 334:» e6ef0070 |
218 ; DIS: 33c:» e6ef1071 | 222 ; DIS: 338:» e6ef1071 |
219 ; DIS: 340:» e730f110 | 223 ; DIS: 33c:» e730f110 |
220 ; DIS: 35c:» e6ef0070 | 224 ; DIS: 358:» e6ef0070 |
221 ; DIS: 360:» e6ef1071 | 225 ; DIS: 35c:» e6ef1071 |
222 ; DIS: 364:» e730f110 | 226 ; DIS: 360:» e730f110 |
223 ; DIS: 380:» e6ef0070 | 227 ; DIS: 37c:» e6ef0070 |
224 ; DIS: 384:» e6ef1071 | 228 ; DIS: 380:» e6ef1071 |
225 ; DIS: 388:» e730f110 | 229 ; DIS: 384:» e730f110 |
226 ; DIS: 3a4:» e6ef0070 | 230 ; DIS: 3a0:» e6ef0070 |
227 ; DIS: 3a8:» e6ef1071 | 231 ; DIS: 3a4:» e6ef1071 |
228 ; DIS: 3ac:» e730f110 | 232 ; DIS: 3a8:» e730f110 |
229 ; DIS: 3c8:» e6ef0070 | 233 ; DIS: 3c4:» e6ef0070 |
230 ; DIS: 3cc:» e6ef1071 | 234 ; DIS: 3c8:» e6ef1071 |
231 ; DIS: 3d0:» e730f110 | 235 ; DIS: 3cc:» e730f110 |
232 ; DIS: 3ec:» e6ef0070 | 236 ; DIS: 3e8:» e6ef0070 |
233 ; DIS: 3f0:» e6ef1071 | 237 ; DIS: 3ec:» e6ef1071 |
234 ; DIS: 3f4:» e730f110 | 238 ; DIS: 3f0:» e730f110 |
235 ; DIS: 410:» e6ef0070 | 239 ; DIS: 40c:» e6ef0070 |
236 ; DIS: 414:» e6ef1071 | 240 ; DIS: 410:» e6ef1071 |
237 ; DIS: 418:» e730f110 | 241 ; DIS: 414:» e730f110 |
238 ; DIS: 434:» e6ef0070 | 242 ; DIS: 430:» e6ef0070 |
239 ; DIS: 438:» e6ef1071 | 243 ; DIS: 434:» e6ef1071 |
240 ; DIS: 43c:» e730f110 | 244 ; DIS: 438:» e730f110 |
241 | 245 |
242 ; IASM-NOT: uxtb | 246 ; IASM-NOT: uxtb |
243 ; IASM-NOT: udiv | 247 ; IASM-NOT: udiv |
244 | 248 |
245 ret <16 x i8> %res | 249 ret <16 x i8> %res |
246 } | 250 } |
OLD | NEW |