ARM32 vector division lowering.

src/IceTargetLoweringARM32.cpp

Index: src/IceTargetLoweringARM32.cpp
diff --git a/src/IceTargetLoweringARM32.cpp b/src/IceTargetLoweringARM32.cpp
index 099ceb26c9f20b92da1720bfab51501cd20fbd30..c1abc9a872a8b055dda37332c754dcaa8b3517cd 100644
--- a/src/IceTargetLoweringARM32.cpp
+++ b/src/IceTargetLoweringARM32.cpp
@@ -430,6 +430,18 @@ void TargetARM32::genTargetHelperCallFor(Inst *Instr) {
     const Type DestTy = Dest->getType();
     const InstArithmetic::OpKind Op =
         llvm::cast<InstArithmetic>(Instr)->getOp();
+    if (isVectorType(DestTy)) {
+      switch (Op) {
+      default:
+        break;
+      case InstArithmetic::Fdiv:
+      case InstArithmetic::Udiv:
+      case InstArithmetic::Sdiv:
+        scalarizeArithmetic(Op, Dest, Instr->getSrc(0), Instr->getSrc(1));
+        Instr->setDeleted();
+        return;
+      }
+    }
     switch (DestTy) {
     default:
       return;
@@ -2015,7 +2027,7 @@ void TargetARM32::div0Check(Type Ty, Operand *SrcLo, Operand *SrcHi) {
   Variable *SrcLoReg = legalizeToReg(SrcLo);
   switch (Ty) {
   default:
-    llvm::report_fatal_error("Unexpected type");
+    llvm_unreachable(("Unexpected type in div0Check: " + typeIceString(Ty)).c_str());
   case IceType_i8:
   case IceType_i16: {
     Operand *ShAmtImm = shAmtImm(32 - getScalarIntBitWidth(Ty));
@@ -5508,7 +5520,8 @@ void TargetARM32::prelowerPhis() {
 Variable *TargetARM32::makeVectorOfZeros(Type Ty, int32_t RegNum) {
   Variable *Reg = makeReg(Ty, RegNum);
   Context.insert<InstFakeDef>(Reg);
-  UnimplementedError(Func->getContext()->getFlags());
+  assert(isVectorType(Ty));
+  _veor(Reg, Reg, Reg);
   return Reg;
 }