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| 1 ; Show that we know how to translate vector division instructions. |
| 2 |
| 3 ; REQUIRES: allow_dump |
| 4 |
| 5 ; Compile using standalone assembler. |
| 6 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 -mattr=hwdiv-arm \ |
| 7 ; RUN: | FileCheck %s --check-prefix=ASM |
| 8 |
| 9 ; Show bytes in assembled standalone code. |
| 10 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \ |
| 11 ; RUN: --args -O2 -mattr=hwdiv-arm \ |
| 12 ; RUN: | FileCheck %s --check-prefix=DIS |
| 13 |
| 14 ; Compile using integrated assembler. |
| 15 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 -mattr=hwdiv-arm \ |
| 16 ; RUN: | FileCheck %s --check-prefix=IASM |
| 17 |
| 18 ; Show bytes in assembled integrated code. |
| 19 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \ |
| 20 ; RUN: --args -O2 -mattr=hwdiv-arm \ |
| 21 ; RUN: | FileCheck %s --check-prefix=DIS |
| 22 |
| 23 define internal <4 x float> @testVdivFloat4(<4 x float> %v1, <4 x float> %v2) { |
| 24 ; ASM-LABEL: testVdivFloat4: |
| 25 ; DIS-LABEL: 00000000 <testVdivFloat4>: |
| 26 ; IASM-LABEL: testVdivFloat4: |
| 27 |
| 28 entry: |
| 29 %res = fdiv <4 x float> %v1, %v2 |
| 30 |
| 31 ; TODO(eholk): this code could be a lot better. Fix the code generator |
| 32 ; and update the test. Same for the rest of the tests. |
| 33 |
| 34 ; ASM: vdiv.f32 s8, s8, s9 |
| 35 ; ASM: vdiv.f32 s8, s8, s9 |
| 36 ; ASM: vdiv.f32 s8, s8, s9 |
| 37 ; ASM: vdiv.f32 s0, s0, s4 |
| 38 |
| 39 ; DIS: 8: ee844a24 |
| 40 ; DIS: 1c: ee844a24 |
| 41 ; DIS: 2c: ee844a24 |
| 42 ; DIS: 3c: ee800a02 |
| 43 |
| 44 ; IASM-NOT: vdiv |
| 45 |
| 46 ret <4 x float> %res |
| 47 } |
| 48 |
| 49 define internal <4 x i32> @testVdiv4i32(<4 x i32> %v1, <4 x i32> %v2) { |
| 50 ; ASM-LABEL: testVdiv4i32: |
| 51 ; DIS-LABEL: 00000050 <testVdiv4i32>: |
| 52 ; IASM-LABEL: testVdiv4i32: |
| 53 |
| 54 entry: |
| 55 %res = udiv <4 x i32> %v1, %v2 |
| 56 |
| 57 ; ASM: udiv r0, r0, r1 |
| 58 ; ASM: udiv r0, r0, r1 |
| 59 ; ASM: udiv r0, r0, r1 |
| 60 ; ASM: udiv r0, r0, r1 |
| 61 |
| 62 ; DIS: 64: e730f110 |
| 63 ; DIS: 84: e730f110 |
| 64 ; DIS: a0: e730f110 |
| 65 ; DIS: bc: e730f110 |
| 66 |
| 67 ; IASM-NOT: udiv |
| 68 |
| 69 ret <4 x i32> %res |
| 70 } |
| 71 |
| 72 define internal <8 x i16> @testVdiv8i16(<8 x i16> %v1, <8 x i16> %v2) { |
| 73 ; ASM-LABEL: testVdiv8i16: |
| 74 ; DIS-LABEL: 000000d0 <testVdiv8i16>: |
| 75 ; IASM-LABEL: testVdiv8i16: |
| 76 |
| 77 entry: |
| 78 %res = udiv <8 x i16> %v1, %v2 |
| 79 |
| 80 ; ASM: uxth r0, r0 |
| 81 ; ASM: uxth r1, r1 |
| 82 ; ASM: udiv r0, r0, r1 |
| 83 ; ASM: uxth r0, r0 |
| 84 ; ASM: uxth r1, r1 |
| 85 ; ASM: udiv r0, r0, r1 |
| 86 ; ASM: uxth r0, r0 |
| 87 ; ASM: uxth r1, r1 |
| 88 ; ASM: udiv r0, r0, r1 |
| 89 ; ASM: uxth r0, r0 |
| 90 ; ASM: uxth r1, r1 |
| 91 ; ASM: udiv r0, r0, r1 |
| 92 ; ASM: uxth r0, r0 |
| 93 ; ASM: uxth r1, r1 |
| 94 ; ASM: udiv r0, r0, r1 |
| 95 ; ASM: uxth r0, r0 |
| 96 ; ASM: uxth r1, r1 |
| 97 ; ASM: udiv r0, r0, r1 |
| 98 ; ASM: uxth r0, r0 |
| 99 ; ASM: uxth r1, r1 |
| 100 ; ASM: udiv r0, r0, r1 |
| 101 ; ASM: uxth r0, r0 |
| 102 ; ASM: uxth r1, r1 |
| 103 ; ASM: udiv r0, r0, r1 |
| 104 |
| 105 ; DIS: e4: e6ff0070 |
| 106 ; DIS: e8: e6ff1071 |
| 107 ; DIS: ec: e730f110 |
| 108 ; DIS: 10c: e6ff0070 |
| 109 ; DIS: 110: e6ff1071 |
| 110 ; DIS: 114: e730f110 |
| 111 ; DIS: 130: e6ff0070 |
| 112 ; DIS: 134: e6ff1071 |
| 113 ; DIS: 138: e730f110 |
| 114 ; DIS: 154: e6ff0070 |
| 115 ; DIS: 158: e6ff1071 |
| 116 ; DIS: 15c: e730f110 |
| 117 ; DIS: 178: e6ff0070 |
| 118 ; DIS: 17c: e6ff1071 |
| 119 ; DIS: 180: e730f110 |
| 120 ; DIS: 19c: e6ff0070 |
| 121 ; DIS: 1a0: e6ff1071 |
| 122 ; DIS: 1a4: e730f110 |
| 123 ; DIS: 1c0: e6ff0070 |
| 124 ; DIS: 1c4: e6ff1071 |
| 125 ; DIS: 1c8: e730f110 |
| 126 ; DIS: 1e4: e6ff0070 |
| 127 ; DIS: 1e8: e6ff1071 |
| 128 ; DIS: 1ec: e730f110 |
| 129 |
| 130 ; IASM-NOT: uxth |
| 131 ; IASM-NOT: udiv |
| 132 |
| 133 ret <8 x i16> %res |
| 134 } |
| 135 |
| 136 define internal <16 x i8> @testVdiv16i8(<16 x i8> %v1, <16 x i8> %v2) { |
| 137 ; ASM-LABEL: testVdiv16i8: |
| 138 ; DIS-LABEL: 00000200 <testVdiv16i8>: |
| 139 ; IASM-LABEL: testVdiv16i8: |
| 140 |
| 141 entry: |
| 142 %res = udiv <16 x i8> %v1, %v2 |
| 143 |
| 144 ; ASM: uxtb r0, r0 |
| 145 ; ASM: uxtb r1, r1 |
| 146 ; ASM: udiv r0, r0, r1 |
| 147 ; ASM: uxtb r0, r0 |
| 148 ; ASM: uxtb r1, r1 |
| 149 ; ASM: udiv r0, r0, r1 |
| 150 ; ASM: uxtb r0, r0 |
| 151 ; ASM: uxtb r1, r1 |
| 152 ; ASM: udiv r0, r0, r1 |
| 153 ; ASM: uxtb r0, r0 |
| 154 ; ASM: uxtb r1, r1 |
| 155 ; ASM: udiv r0, r0, r1 |
| 156 ; ASM: uxtb r0, r0 |
| 157 ; ASM: uxtb r1, r1 |
| 158 ; ASM: udiv r0, r0, r1 |
| 159 ; ASM: uxtb r0, r0 |
| 160 ; ASM: uxtb r1, r1 |
| 161 ; ASM: udiv r0, r0, r1 |
| 162 ; ASM: uxtb r0, r0 |
| 163 ; ASM: uxtb r1, r1 |
| 164 ; ASM: udiv r0, r0, r1 |
| 165 ; ASM: uxtb r0, r0 |
| 166 ; ASM: uxtb r1, r1 |
| 167 ; ASM: udiv r0, r0, r1 |
| 168 ; ASM: uxtb r0, r0 |
| 169 ; ASM: uxtb r1, r1 |
| 170 ; ASM: udiv r0, r0, r1 |
| 171 ; ASM: uxtb r0, r0 |
| 172 ; ASM: uxtb r1, r1 |
| 173 ; ASM: udiv r0, r0, r1 |
| 174 ; ASM: uxtb r0, r0 |
| 175 ; ASM: uxtb r1, r1 |
| 176 ; ASM: udiv r0, r0, r1 |
| 177 ; ASM: uxtb r0, r0 |
| 178 ; ASM: uxtb r1, r1 |
| 179 ; ASM: udiv r0, r0, r1 |
| 180 ; ASM: uxtb r0, r0 |
| 181 ; ASM: uxtb r1, r1 |
| 182 ; ASM: udiv r0, r0, r1 |
| 183 ; ASM: uxtb r0, r0 |
| 184 ; ASM: uxtb r1, r1 |
| 185 ; ASM: udiv r0, r0, r1 |
| 186 ; ASM: uxtb r0, r0 |
| 187 ; ASM: uxtb r1, r1 |
| 188 ; ASM: udiv r0, r0, r1 |
| 189 ; ASM: uxtb r0, r0 |
| 190 ; ASM: uxtb r1, r1 |
| 191 ; ASM: udiv r0, r0, r1 |
| 192 |
| 193 ; DIS: 214: e6ef0070 |
| 194 ; DIS: 218: e6ef1071 |
| 195 ; DIS: 21c: e730f110 |
| 196 ; DIS: 23c: e6ef0070 |
| 197 ; DIS: 240: e6ef1071 |
| 198 ; DIS: 244: e730f110 |
| 199 ; DIS: 260: e6ef0070 |
| 200 ; DIS: 264: e6ef1071 |
| 201 ; DIS: 268: e730f110 |
| 202 ; DIS: 284: e6ef0070 |
| 203 ; DIS: 288: e6ef1071 |
| 204 ; DIS: 28c: e730f110 |
| 205 ; DIS: 2a8: e6ef0070 |
| 206 ; DIS: 2ac: e6ef1071 |
| 207 ; DIS: 2b0: e730f110 |
| 208 ; DIS: 2cc: e6ef0070 |
| 209 ; DIS: 2d0: e6ef1071 |
| 210 ; DIS: 2d4: e730f110 |
| 211 ; DIS: 2f0: e6ef0070 |
| 212 ; DIS: 2f4: e6ef1071 |
| 213 ; DIS: 2f8: e730f110 |
| 214 ; DIS: 314: e6ef0070 |
| 215 ; DIS: 318: e6ef1071 |
| 216 ; DIS: 31c: e730f110 |
| 217 ; DIS: 338: e6ef0070 |
| 218 ; DIS: 33c: e6ef1071 |
| 219 ; DIS: 340: e730f110 |
| 220 ; DIS: 35c: e6ef0070 |
| 221 ; DIS: 360: e6ef1071 |
| 222 ; DIS: 364: e730f110 |
| 223 ; DIS: 380: e6ef0070 |
| 224 ; DIS: 384: e6ef1071 |
| 225 ; DIS: 388: e730f110 |
| 226 ; DIS: 3a4: e6ef0070 |
| 227 ; DIS: 3a8: e6ef1071 |
| 228 ; DIS: 3ac: e730f110 |
| 229 ; DIS: 3c8: e6ef0070 |
| 230 ; DIS: 3cc: e6ef1071 |
| 231 ; DIS: 3d0: e730f110 |
| 232 ; DIS: 3ec: e6ef0070 |
| 233 ; DIS: 3f0: e6ef1071 |
| 234 ; DIS: 3f4: e730f110 |
| 235 ; DIS: 410: e6ef0070 |
| 236 ; DIS: 414: e6ef1071 |
| 237 ; DIS: 418: e730f110 |
| 238 ; DIS: 434: e6ef0070 |
| 239 ; DIS: 438: e6ef1071 |
| 240 ; DIS: 43c: e730f110 |
| 241 |
| 242 ; IASM-NOT: uxtb |
| 243 ; IASM-NOT: udiv |
| 244 |
| 245 ret <16 x i8> %res |
| 246 } |
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