src/IceTypes.def - Issue 1681003002: ARM32 vector division lowering.

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Issue 1681003002: ARM32 vector division lowering. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master

Patch Set: Created 4 years, 10 months ago

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1 //===- subzero/src/IceTypes.def - X-macros for ICE types --------- C++ --===//	1 //===- subzero/src/IceTypes.def - X-macros for ICE types --------- C++ --===//

2 //	2 //

3 // The Subzero Code Generator	3 // The Subzero Code Generator

4 //	4 //

5 // This file is distributed under the University of Illinois Open Source	5 // This file is distributed under the University of Illinois Open Source

6 // License. See LICENSE.TXT for details.	6 // License. See LICENSE.TXT for details.

7 //	7 //

8 //===----------------------------------------------------------------------===//	8 //===----------------------------------------------------------------------===//

9 //	9 //

10 // This file defines properties of ICE primitive types in the form of x-macros.	10 // This file defines properties of ICE primitive types in the form of x-macros.

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38 /* register class string */ \	38 /* register class string */ \

39 X(void, -1, 0, 1, void, "void", "void") \	39 X(void, -1, 0, 1, void, "void", "void") \

40 X(i1, 0, 1, 1, i1, "i1", "i1") \	40 X(i1, 0, 1, 1, i1, "i1", "i1") \

41 X(i8, 0, 1, 1, i8, "i8", "i8") \	41 X(i8, 0, 1, 1, i8, "i8", "i8") \

42 X(i16, 1, 1, 1, i16, "i16", "i16") \	42 X(i16, 1, 1, 1, i16, "i16", "i16") \

43 X(i32, 2, 1, 1, i32, "i32", "i32") \	43 X(i32, 2, 1, 1, i32, "i32", "i32") \

44 X(i64, 3, 1, 1, i64, "i64", "i64") \	44 X(i64, 3, 1, 1, i64, "i64", "i64") \

45 X(f32, 2, 4, 1, f32, "float", "f32") \	45 X(f32, 2, 4, 1, f32, "float", "f32") \

46 X(f64, 3, 8, 1, f64, "double", "f64") \	46 X(f64, 3, 8, 1, f64, "double", "f64") \

47 X(v4i1, 4, 1, 4, i1, "<4 x i1>", "v4i1") \	47 X(v4i1, 4, 1, 4, i1, "<4 x i1>", "v4i1") \

48 X(v8i1, 4, 1, 8, i1, "<8 x i1>", "v8ii") \	48 X(v8i1, 4, 1, 8, i1, "<8 x i1>", "v8i1") \

49 X(v16i1, 4, 1, 16, i1, "<16 x i1>", "v16i1") \	49 X(v16i1, 4, 1, 16, i1, "<16 x i1>", "v16i1") \

50 X(v16i8, 4, 1, 16, i8, "<16 x i8>", "v16i8") \	50 X(v16i8, 4, 1, 16, i8, "<16 x i8>", "v16i8") \

51 X(v8i16, 4, 2, 8, i16, "<8 x i16>", "v8i16") \	51 X(v8i16, 4, 2, 8, i16, "<8 x i16>", "v8i16") \

52 X(v4i32, 4, 4, 4, i32, "<4 x i32>", "v4i32") \	52 X(v4i32, 4, 4, 4, i32, "<4 x i32>", "v4i32") \

53 X(v4f32, 4, 4, 4, f32, "<4 x float>", "v4f32") \	53 X(v4f32, 4, 4, 4, f32, "<4 x float>", "v4f32") \

54 //#define X(tag, sizeLog2, align, elts, elty, str, rcstr)	54 //#define X(tag, sizeLog2, align, elts, elty, str, rcstr)

55	55

56 // Dictionary:	56 // Dictionary:

57 // V - Is vector type.	57 // V - Is vector type.

58 // I - Is integer value (scalar or vector).	58 // I - Is integer value (scalar or vector).

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76 X(v8i1, 1, 1, 0, 0, 0, 1, v8i1) \	76 X(v8i1, 1, 1, 0, 0, 0, 1, v8i1) \

77 X(v16i1, 1, 1, 0, 0, 0, 1, v16i1) \	77 X(v16i1, 1, 1, 0, 0, 0, 1, v16i1) \

78 X(v16i8, 1, 1, 0, 1, 1, 1, v16i1) \	78 X(v16i8, 1, 1, 0, 1, 1, 1, v16i1) \

79 X(v8i16, 1, 1, 0, 1, 1, 1, v8i1) \	79 X(v8i16, 1, 1, 0, 1, 1, 1, v8i1) \

80 X(v4i32, 1, 1, 0, 1, 1, 1, v4i1) \	80 X(v4i32, 1, 1, 0, 1, 1, 1, v4i1) \

81 X(v4f32, 1, 0, 1, 0, 1, 1, v4i1) \	81 X(v4f32, 1, 0, 1, 0, 1, 1, v4i1) \

82 //#define X(tag, IsVec, IsInt, IsFloat, IsIntArith, IsLoadStore, IsParam, \	82 //#define X(tag, IsVec, IsInt, IsFloat, IsIntArith, IsLoadStore, IsParam, \

83 // CompareResult)	83 // CompareResult)

84	84

85 #endif // SUBZERO_SRC_ICETYPES_DEF	85 #endif // SUBZERO_SRC_ICETYPES_DEF

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