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1 //===- subzero/src/IceTargetLoweringX86Base.h - x86 lowering ----*- C++ -*-===// | 1 //===- subzero/src/IceTargetLoweringX86Base.h - x86 lowering ----*- C++ -*-===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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336 /// true if the flags contain the result of a comparison with the Comparison. | 336 /// true if the flags contain the result of a comparison with the Comparison. |
337 void lowerCaseCluster(const CaseCluster &Case, Operand *Src0, bool DoneCmp, | 337 void lowerCaseCluster(const CaseCluster &Case, Operand *Src0, bool DoneCmp, |
338 CfgNode *DefaultLabel = nullptr); | 338 CfgNode *DefaultLabel = nullptr); |
339 | 339 |
340 using LowerBinOp = void (TargetX86Base::*)(Variable *, Operand *); | 340 using LowerBinOp = void (TargetX86Base::*)(Variable *, Operand *); |
341 void expandAtomicRMWAsCmpxchg(LowerBinOp op_lo, LowerBinOp op_hi, | 341 void expandAtomicRMWAsCmpxchg(LowerBinOp op_lo, LowerBinOp op_hi, |
342 Variable *Dest, Operand *Ptr, Operand *Val); | 342 Variable *Dest, Operand *Ptr, Operand *Val); |
343 | 343 |
344 void eliminateNextVectorSextInstruction(Variable *SignExtendedResult); | 344 void eliminateNextVectorSextInstruction(Variable *SignExtendedResult); |
345 | 345 |
346 void scalarizeArithmetic(InstArithmetic::OpKind K, Variable *Dest, | |
347 Operand *Src0, Operand *Src1); | |
348 | |
349 void emitGetIP(CfgNode *Node) { | 346 void emitGetIP(CfgNode *Node) { |
350 dispatchToConcrete(&Traits::ConcreteTarget::emitGetIP, std::move(Node)); | 347 dispatchToConcrete(&Traits::ConcreteTarget::emitGetIP, std::move(Node)); |
351 } | 348 } |
352 /// Emit a sandboxed return sequence rather than a return. | 349 /// Emit a sandboxed return sequence rather than a return. |
353 void emitSandboxedReturn() { | 350 void emitSandboxedReturn() { |
354 dispatchToConcrete(&Traits::ConcreteTarget::emitSandboxedReturn); | 351 dispatchToConcrete(&Traits::ConcreteTarget::emitSandboxedReturn); |
355 } | 352 } |
356 /// Emit just the call instruction (without argument or return variable | 353 /// Emit just the call instruction (without argument or return variable |
357 /// processing), sandboxing if needed. | 354 /// processing), sandboxing if needed. |
358 virtual Inst *emitCallToTarget(Operand *CallTarget, Variable *ReturnReg) = 0; | 355 virtual Inst *emitCallToTarget(Operand *CallTarget, Variable *ReturnReg) = 0; |
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1128 | 1125 |
1129 explicit TargetHeaderX86(GlobalContext *Ctx) : TargetHeaderLowering(Ctx) {} | 1126 explicit TargetHeaderX86(GlobalContext *Ctx) : TargetHeaderLowering(Ctx) {} |
1130 }; | 1127 }; |
1131 | 1128 |
1132 } // end of namespace X86NAMESPACE | 1129 } // end of namespace X86NAMESPACE |
1133 } // end of namespace Ice | 1130 } // end of namespace Ice |
1134 | 1131 |
1135 #include "IceTargetLoweringX86BaseImpl.h" | 1132 #include "IceTargetLoweringX86BaseImpl.h" |
1136 | 1133 |
1137 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASE_H | 1134 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASE_H |
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