ARM32 vector division lowering.

src/IceTargetLoweringX86Base.h

 //===- subzero/src/IceTargetLoweringX86Base.h - x86 lowering ----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 325 matching lines @@
   /// true if the flags contain the result of a comparison with the Comparison.
   void lowerCaseCluster(const CaseCluster &Case, Operand *Src0, bool DoneCmp,
                         CfgNode *DefaultLabel = nullptr);
 
   using LowerBinOp = void (TargetX86Base::*)(Variable *, Operand *);
   void expandAtomicRMWAsCmpxchg(LowerBinOp op_lo, LowerBinOp op_hi,
                                 Variable *Dest, Operand *Ptr, Operand *Val);
 
   void eliminateNextVectorSextInstruction(Variable *SignExtendedResult);
 
-  void scalarizeArithmetic(InstArithmetic::OpKind K, Variable *Dest,
-                           Operand *Src0, Operand *Src1);
-
   void emitGetIP(CfgNode *Node) {
     dispatchToConcrete(&Traits::ConcreteTarget::emitGetIP, std::move(Node));
   }
   /// Emit a sandboxed return sequence rather than a return.
   void emitSandboxedReturn() {
     dispatchToConcrete(&Traits::ConcreteTarget::emitSandboxedReturn);
   }
   /// Emit just the call instruction (without argument or return variable
   /// processing), sandboxing if needed.
   virtual Inst *emitCallToTarget(Operand *CallTarget, Variable *ReturnReg) = 0;
@@ skipping 769 matching lines @@
 
   explicit TargetHeaderX86(GlobalContext *Ctx) : TargetHeaderLowering(Ctx) {}
 };
 
 } // end of namespace X86NAMESPACE
 } // end of namespace Ice
 
 #include "IceTargetLoweringX86BaseImpl.h"
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASE_H