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1 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===// | 1 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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423 constexpr bool IsTargetHelperCall = true; | 423 constexpr bool IsTargetHelperCall = true; |
424 | 424 |
425 switch (Instr->getKind()) { | 425 switch (Instr->getKind()) { |
426 default: | 426 default: |
427 return; | 427 return; |
428 case Inst::Arithmetic: { | 428 case Inst::Arithmetic: { |
429 Variable *Dest = Instr->getDest(); | 429 Variable *Dest = Instr->getDest(); |
430 const Type DestTy = Dest->getType(); | 430 const Type DestTy = Dest->getType(); |
431 const InstArithmetic::OpKind Op = | 431 const InstArithmetic::OpKind Op = |
432 llvm::cast<InstArithmetic>(Instr)->getOp(); | 432 llvm::cast<InstArithmetic>(Instr)->getOp(); |
| 433 if (isVectorType(DestTy)) { |
| 434 switch (Op) { |
| 435 default: |
| 436 break; |
| 437 case InstArithmetic::Fdiv: |
| 438 case InstArithmetic::Udiv: |
| 439 case InstArithmetic::Sdiv: |
| 440 scalarizeArithmetic(Op, Dest, Instr->getSrc(0), Instr->getSrc(1)); |
| 441 Instr->setDeleted(); |
| 442 return; |
| 443 } |
| 444 } |
433 switch (DestTy) { | 445 switch (DestTy) { |
434 default: | 446 default: |
435 return; | 447 return; |
436 case IceType_i64: { | 448 case IceType_i64: { |
437 // Technically, ARM has its own aeabi routines, but we can use the | 449 // Technically, ARM has its own aeabi routines, but we can use the |
438 // non-aeabi routine as well. LLVM uses __aeabi_ldivmod for div, but uses | 450 // non-aeabi routine as well. LLVM uses __aeabi_ldivmod for div, but uses |
439 // the more standard __moddi3 for rem. | 451 // the more standard __moddi3 for rem. |
440 Operand *TargetHelper = nullptr; | 452 Operand *TargetHelper = nullptr; |
441 switch (Op) { | 453 switch (Op) { |
442 default: | 454 default: |
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2008 | 2020 |
2009 _mov(Dest, T); | 2021 _mov(Dest, T); |
2010 } | 2022 } |
2011 | 2023 |
2012 void TargetARM32::div0Check(Type Ty, Operand *SrcLo, Operand *SrcHi) { | 2024 void TargetARM32::div0Check(Type Ty, Operand *SrcLo, Operand *SrcHi) { |
2013 if (isGuaranteedNonzeroInt(SrcLo) || isGuaranteedNonzeroInt(SrcHi)) | 2025 if (isGuaranteedNonzeroInt(SrcLo) || isGuaranteedNonzeroInt(SrcHi)) |
2014 return; | 2026 return; |
2015 Variable *SrcLoReg = legalizeToReg(SrcLo); | 2027 Variable *SrcLoReg = legalizeToReg(SrcLo); |
2016 switch (Ty) { | 2028 switch (Ty) { |
2017 default: | 2029 default: |
2018 llvm::report_fatal_error("Unexpected type"); | 2030 llvm_unreachable(("Unexpected type in div0Check: " + typeIceString(Ty)).c_st
r()); |
2019 case IceType_i8: | 2031 case IceType_i8: |
2020 case IceType_i16: { | 2032 case IceType_i16: { |
2021 Operand *ShAmtImm = shAmtImm(32 - getScalarIntBitWidth(Ty)); | 2033 Operand *ShAmtImm = shAmtImm(32 - getScalarIntBitWidth(Ty)); |
2022 Variable *T = makeReg(IceType_i32); | 2034 Variable *T = makeReg(IceType_i32); |
2023 _lsls(T, SrcLoReg, ShAmtImm); | 2035 _lsls(T, SrcLoReg, ShAmtImm); |
2024 Context.insert<InstFakeUse>(T); | 2036 Context.insert<InstFakeUse>(T); |
2025 } break; | 2037 } break; |
2026 case IceType_i32: { | 2038 case IceType_i32: { |
2027 _tst(SrcLoReg, SrcLoReg); | 2039 _tst(SrcLoReg, SrcLoReg); |
2028 break; | 2040 break; |
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5501 _trap(); | 5513 _trap(); |
5502 } | 5514 } |
5503 | 5515 |
5504 void TargetARM32::prelowerPhis() { | 5516 void TargetARM32::prelowerPhis() { |
5505 PhiLowering::prelowerPhis32Bit<TargetARM32>(this, Context.getNode(), Func); | 5517 PhiLowering::prelowerPhis32Bit<TargetARM32>(this, Context.getNode(), Func); |
5506 } | 5518 } |
5507 | 5519 |
5508 Variable *TargetARM32::makeVectorOfZeros(Type Ty, int32_t RegNum) { | 5520 Variable *TargetARM32::makeVectorOfZeros(Type Ty, int32_t RegNum) { |
5509 Variable *Reg = makeReg(Ty, RegNum); | 5521 Variable *Reg = makeReg(Ty, RegNum); |
5510 Context.insert<InstFakeDef>(Reg); | 5522 Context.insert<InstFakeDef>(Reg); |
5511 UnimplementedError(Func->getContext()->getFlags()); | 5523 assert(isVectorType(Ty)); |
| 5524 _veor(Reg, Reg, Reg); |
5512 return Reg; | 5525 return Reg; |
5513 } | 5526 } |
5514 | 5527 |
5515 // Helper for legalize() to emit the right code to lower an operand to a | 5528 // Helper for legalize() to emit the right code to lower an operand to a |
5516 // register of the appropriate type. | 5529 // register of the appropriate type. |
5517 Variable *TargetARM32::copyToReg(Operand *Src, int32_t RegNum) { | 5530 Variable *TargetARM32::copyToReg(Operand *Src, int32_t RegNum) { |
5518 Type Ty = Src->getType(); | 5531 Type Ty = Src->getType(); |
5519 Variable *Reg = makeReg(Ty, RegNum); | 5532 Variable *Reg = makeReg(Ty, RegNum); |
5520 if (auto *Mem = llvm::dyn_cast<OperandARM32Mem>(Src)) { | 5533 if (auto *Mem = llvm::dyn_cast<OperandARM32Mem>(Src)) { |
5521 _ldr(Reg, Mem); | 5534 _ldr(Reg, Mem); |
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6571 Str << ".eabi_attribute 14, 3 @ Tag_ABI_PCS_R9_use: Not used\n"; | 6584 Str << ".eabi_attribute 14, 3 @ Tag_ABI_PCS_R9_use: Not used\n"; |
6572 } | 6585 } |
6573 | 6586 |
6574 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM]; | 6587 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM]; |
6575 llvm::SmallBitVector | 6588 llvm::SmallBitVector |
6576 TargetARM32::TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM]; | 6589 TargetARM32::TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM]; |
6577 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM]; | 6590 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM]; |
6578 | 6591 |
6579 } // end of namespace ARM32 | 6592 } // end of namespace ARM32 |
6580 } // end of namespace Ice | 6593 } // end of namespace Ice |
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