Add insert/extract element to the integrated ARM assembler.

src/IceAssemblerARM32.h

 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 399 matching lines @@
   // ElmtSize = #bits in vector element.
   void vld1qr(size_t ElmtSize, const Operand *OpQd, const Operand *OpRn,
               const TargetInfo &TInfo);
 
   void vld1qr(size_t ElmtSize, const Operand *OpQd, const Operand *OpRn,
               const TargetLowering *Lowering) {
     const TargetInfo TInfo(Lowering);
     vld1qr(ElmtSize, OpQd, OpRn, TInfo);
   }
 
+  // Dn = FpImm
   void vmovd(const Operand *OpDn, const OperandARM32FlexFpImm *OpFpImm,
              CondARM32::Cond Cond);
 
+  // Dd = Dm
   void vmovdd(const Operand *OpDd, const Variable *OpDm, CondARM32::Cond Cond);
 
+  // Dm = Rt:Rt2
   void vmovdrr(const Operand *OpDm, const Operand *OpRt, const Operand *OpRt2,
                CondARM32::Cond Cond);
 
+  // Qd[Index] = Rt
+  void vmovqir(const Operand *OpQd, uint32_t Index, const Operand *OpRt,
+               CondARM32::Cond Cond);
+
+  // Qd[Index] = Sm
+  void vmovqis(const Operand *OpQd, uint32_t Indx, const Operand *OpSm,
+               CondARM32::Cond Cond);
+
+  // Rt = Qm[Index]
+  void vmovrqi(const Operand *OpRt, const Operand *OpQd, uint32_t Index,
+               CondARM32::Cond Cond);
+
+  // Rt:Rt2 = Dm
   void vmovrrd(const Operand *OpRt, const Operand *OpRt2, const Operand *OpDm,
                CondARM32::Cond Cond);
 
+  // Rt = Sn
   void vmovrs(const Operand *OpRt, const Operand *OpSn, CondARM32::Cond Cond);
 
+  // Sn = FpImm
   void vmovs(const Operand *OpSn, const OperandARM32FlexFpImm *OpFpImm,
              CondARM32::Cond Cond);
 
-  void vmovss(const Operand *OpDd, const Variable *OpDm, CondARM32::Cond Cond);
+  // Sd = Sm
+  void vmovss(const Operand *OpSd, const Variable *OpSm, CondARM32::Cond Cond);
 
+  // Sd = Qm[Index]
+  void vmovsqi(const Operand *OpSd, const Operand *OpQm, uint32_t Index,
+               CondARM32::Cond Cond);
+
+  // Sn = Rt
   void vmovsr(const Operand *OpSn, const Operand *OpRt, CondARM32::Cond Cond);
 
   void vmlad(const Operand *OpDd, const Operand *OpDn, const Operand *OpDm,
              CondARM32::Cond Cond);
 
   void vmlas(const Operand *OpSd, const Operand *OpSn, const Operand *OpSm,
              CondARM32::Cond Cond);
 
   void vmlsd(const Operand *OpDd, const Operand *OpDn, const Operand *OpDm,
              CondARM32::Cond Cond);
@@ skipping 186 matching lines @@
   // aa=Align.
   void emitVMem1Op(IValueT Opcode, IValueT Dd, IValueT Rn, IValueT Rm,
                    DRegListSize NumDRegs, size_t ElmtSize, IValueT Align,
                    const char *InstName);
 
   // Pattern cccc011100x1dddd1111mmmm0001nnn where cccc=Cond,
   // x=Opcode, dddd=Rd, nnnn=Rn, mmmm=Rm.
   void emitDivOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, IValueT Rn,
                  IValueT Rm);
 
+  // cccc1110iiiennnntttt1011Njj10000 where cccc=Cond, tttt=Rt, Ndddd=2*Qn=Dn,
+  // iii=Opcode1, jj=Opcode2, Opcode1Opcode2 encodes Index and the
+  // corresponding element size of the vector element, and e=IsExtract.
+  void emitInsertExtractInt(CondARM32::Cond Cond, const Operand *OpQn,
+                            uint32_t Index, const Operand *OpRt, bool IsExtract,
+                            const char *InstName);
+
+  // cccc11101D110000dddd101001M0mmmm where cccc=Cond, ddddD=Sd, and mmmmM=Sm.
+  // Assigns Sd the value of Sm.
+  void emitMoveSS(CondARM32::Cond Cond, IValueT Sd, IValueT Sm);
+
   // Pattern ccccxxxxxxxfnnnnddddssss1001mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
   // mmmm=Rm, ssss=Rs, f=SetFlags and xxxxxxx=Opcode.
   void emitMulOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, IValueT Rn,
                  IValueT Rm, IValueT Rs, bool SetFlags);
 
   // Pattern cccc0001101s0000ddddxxxxxtt0mmmm where cccc=Cond, s=SetFlags,
   // dddd=Rd, mmmm=Rm, tt=Shift, and xxxxx is defined by OpSrc1. OpSrc1 defines
   // either xxxxx=Imm5, or xxxxx=ssss0 where ssss=Rs.
   void emitShift(const CondARM32::Cond Cond,
                  const OperandARM32::ShiftKind Shift, const Operand *OpRd,
@@ skipping 51 matching lines @@
 
   void emitVFPsss(CondARM32::Cond Cond, IValueT Opcode, const Operand *OpSd,
                   const Operand *OpSn, const Operand *OpSm,
                   const char *InstName);
 };
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H