Add insert/extract element to the integrated ARM assembler.

src/IceInstARM32.cpp

 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 1047 matching lines @@
   }
 
   if (Src64 == nullptr) {
     addSource(Src);
   } else {
     addSource(Src64->getLo());
     addSource(Src64->getHi());
   }
 }
 
+namespace {
+
 // These next two functions find the D register that maps to the half of the Q
 // register that this instruction is accessing.
 Register getDRegister(const Variable *Src, uint32_t Index) {
   assert(Src->hasReg());
   const auto SrcReg = static_cast<Register>(Src->getRegNum());
 
   const RegARM32::RegTableType &SrcEntry = RegARM32::RegTable[SrcReg];
   assert(SrcEntry.IsVec128);
 
   const uint32_t NumElements = typeNumElements(Src->getType());
@@ skipping 37 matching lines @@
   assert(SrcReg < RegARM32::Reg_q8);
 
   // This part assumes the register alias list goes q0, d0, d1, s0, s1, s2, s3.
   assert(Index < 4);
 
   // TODO(jpp): find a way to do this that doesn't rely on ordering of the alias
   // list.
   return static_cast<Register>(RegARM32::RegTable[SrcReg].Aliases[Index + 3]);
 }
 
+} // end of anonymous namespace
+
 void InstARM32Extract::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   const Type DestTy = getDest()->getType();
 
   const auto *Src = llvm::cast<Variable>(getSrc(0));
 
   if (isIntegerType(DestTy)) {
     Str << "\t"
         << "vmov" << getPredicate();
     const uint32_t BitSize = typeWidthInBytes(DestTy) * CHAR_BIT;
@@ skipping 18 matching lines @@
     Str << "\t"
         << "vmov" << getPredicate() << ".f32"
         << "\t";
     getDest()->emit(Func);
     Str << ", " << RegARM32::RegTable[SrcReg].Name;
   } else {
     assert(false && "Invalid extract type");
   }
 }
 
+void InstARM32Extract::emitIAS(const Cfg *Func) const {
+  const Operand *Dest = getDest();
+  const Type DestTy = Dest->getType();
+  const Operand *Src = getSrc(0);
+  const Type SrcTy = Src->getType();
+  assert(isVectorType(SrcTy));
+  assert(DestTy == typeElementType(SrcTy));
+  auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
+  if (isIntegerType(DestTy)) {
+    Asm->vmovrqi(Dest, Src, Index, getPredicate());
+    assert(!Asm->needsTextFixup());
+    return;
+  }
+  assert(isFloatingType(DestTy));
+  Asm->vmovsqi(Dest, Src, Index, getPredicate());
+  assert(!Asm->needsTextFixup());
+}
+
 void InstARM32Insert::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   const Variable *Dest = getDest();
   const Type DestTy = getDest()->getType();
 
   const auto *Src = llvm::cast<Variable>(getSrc(0));
 
   if (isIntegerType(DestTy)) {
     Str << "\t"
         << "vmov" << getPredicate();
@@ skipping 11 matching lines @@
         << "vmov" << getPredicate() << ".f32"
         << "\t";
     const Register DestReg = getSRegister(Dest, Index);
     Str << RegARM32::RegTable[DestReg].Name << ", ";
     Src->emit(Func);
   } else {
     assert(false && "Invalid insert type");
   }
 }
 
+void InstARM32Insert::emitIAS(const Cfg *Func) const {
+  const Variable *Dest = getDest();
+  const Type DestTy = getDest()->getType();
+  const Operand *Src = getSrc(0);
+  const Type SrcTy = Src->getType();
+  assert(isVectorType(DestTy));
+  assert(typeElementType(DestTy) == SrcTy);
+  auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
+  if (isIntegerType(SrcTy)) {
+    const Operand *Src = getSrc(0);
+    Asm->vmovqir(Dest, Index, Src, getPredicate());
+    assert(!Asm->needsTextFixup());
+    return;
+  }
+  assert(isFloatingType(SrcTy));
+  Asm->vmovqis(Dest, Index, Src, getPredicate());
+  assert(!Asm->needsTextFixup());
+}
+
 template <InstARM32::InstKindARM32 K>
 void InstARM32CmpLike<K>::emitIAS(const Cfg *Func) const {
   emitUsingTextFixup(Func);
 }
 
 template <> void InstARM32Cmn::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 2);
   auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
   Asm->cmn(getSrc(0), getSrc(1), getPredicate());
   if (Asm->needsTextFixup())
@@ skipping 1508 matching lines @@
 
 template class InstARM32FourAddrGPR<InstARM32::Mla>;
 template class InstARM32FourAddrGPR<InstARM32::Mls>;
 
 template class InstARM32CmpLike<InstARM32::Cmn>;
 template class InstARM32CmpLike<InstARM32::Cmp>;
 template class InstARM32CmpLike<InstARM32::Tst>;
 
 } // end of namespace ARM32
 } // end of namespace Ice