Add insert/extract element to the integrated ARM assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 140 matching lines @@
   case IceType_f32:
     return 0;
   case IceType_i16:
     return 1;
   case IceType_i32:
     return 2;
   case IceType_i64:
     return 3;
   default:
     llvm::report_fatal_error("SIMD op: Don't understand element type " +
-                             std::string(typeString(ElmtTy)));
+                             typeIceString(ElmtTy));
   }
 }
 
 IValueT encodeShift(OperandARM32::ShiftKind Shift) {
   // Follows encoding in ARM section A8.4.1 "Constant shifts".
   switch (Shift) {
   case OperandARM32::kNoShift:
   case OperandARM32::LSL:
     return 0; // 0b00
   case OperandARM32::LSR:
@@ skipping 34 matching lines @@
 }
 
 IValueT getEncodedDRegNum(const Variable *Var) {
   return RegARM32::getEncodedDReg(Var->getRegNum());
 }
 
 IValueT getEncodedQRegNum(const Variable *Var) {
   return RegARM32::getEncodedQReg(Var->getRegNum());
 }
 
-IValueT mapQRegToDReg(IValueT EncodedQReg) { return EncodedQReg << 1; }
+IValueT mapQRegToDReg(IValueT EncodedQReg) {
+  IValueT DReg = EncodedQReg << 1;
+  assert(DReg < RegARM32::getNumDRegs());
+  return DReg;
+}
+
+IValueT mapQRegToSReg(IValueT EncodedQReg) {
+  IValueT SReg = EncodedQReg << 2;
+  assert(SReg < RegARM32::getNumSRegs());
+  return SReg;
+}
 
 IValueT getYInRegXXXXY(IValueT RegXXXXY) { return RegXXXXY & 0x1; }
 
 IValueT getXXXXInRegXXXXY(IValueT RegXXXXY) { return RegXXXXY >> 1; }
 
 IValueT getYInRegYXXXX(IValueT RegYXXXX) { return RegYXXXX >> 4; }
 
 IValueT getXXXXInRegYXXXX(IValueT RegYXXXX) { return RegYXXXX & 0x0f; }
 
 // Defines layouts of an operand representing a (register) memory address,
@@ skipping 777 matching lines @@
   assert(Rn < RegARM32::getNumGPRegs());
   assert(Rm < RegARM32::getNumGPRegs());
   assert(CondARM32::isDefined(Cond));
   const IValueT Encoding = Opcode | (encodeCondition(Cond) << kConditionShift) |
                            (Rn << kDivRnShift) | (Rd << kDivRdShift) | B26 |
                            B25 | B24 | B20 | B15 | B14 | B13 | B12 | B4 |
                            (Rm << kDivRmShift);
   emitInst(Encoding);
 }
 
+void AssemblerARM32::emitInsertExtractInt(CondARM32::Cond Cond,
+                                          const Operand *OpQn, uint32_t Index,
+                                          const Operand *OpRt, bool IsExtract,
+                                          const char *InstName) {
+  IValueT Rt = encodeGPRegister(OpRt, "Rt", InstName);

[John, 2016/02/10 20:25:38]

const

[Karl, 2016/02/10 21:31:02]

Done.

+  IValueT Dn = mapQRegToDReg(encodeQRegister(OpQn, "Qn", InstName));
+  assert(Rt != RegARM32::Encoded_Reg_pc);
+  assert(Rt != RegARM32::Encoded_Reg_sp);
+  assert(CondARM32::isDefined(Cond));
+  const uint32_t BitSize = typeWidthInBytes(OpRt->getType()) * CHAR_BIT;
+  IValueT Opcode1 = 0;
+  IValueT Opcode2 = 0;
+  switch (BitSize) {
+  default:
+    llvm::report_fatal_error(std::string(InstName) +
+                             ": Unable to process type " +
+                             typeIceString(OpRt->getType()));
+  case 8:
+    assert(Index < 16);
+    Dn = Dn + mask(Index, 3, 1);

[John, 2016/02/10 20:25:38]

perhaps | instead of +?

[Karl, 2016/02/10 21:31:03]

Actually, we want an add here. We increment Dn to the right register, based on
the index value.

Then again, since there are only two registers, using | makes sense. Changing to
|.

+    Opcode1 = B1 | mask(Index, 2, 1);
+    Opcode2 = mask(Index, 0, 2);
+    break;
+  case 16:
+    assert(Index < 8);
+    Dn = Dn + mask(Index, 2, 1);
+    Opcode1 = mask(Index, 1, 1);
+    Opcode2 = (mask(Index, 0, 1) << 1) | B0;
+    break;
+  case 32:
+    assert(Index < 4);
+    Dn = Dn + mask(Index, 1, 1);
+    Opcode1 = mask(Index, 0, 1);
+    break;
+  }
+  const IValueT Encoding = B27 | B26 | B25 | B11 | B9 | B8 | B4 |
+                           (encodeCondition(Cond) << kConditionShift) |
+                           (Opcode1 << 21) |
+                           (getXXXXInRegYXXXX(Dn) << kRnShift) | (Rt << 12) |
+                           (encodeBool(IsExtract) << 20) |
+                           (getYInRegYXXXX(Dn) << 7) | (Opcode2 << 5);
+  emitInst(Encoding);
+}
+
+void AssemblerARM32::emitMoveSS(CondARM32::Cond Cond, IValueT Sd, IValueT Sm) {
+  // VMOV (register) - ARM section A8.8.340, encoding A2:
+  //   vmov<c>.f32 <Sd>, <Sm>
+  //
+  // cccc11101D110000dddd101001M0mmmm where cccc=Cond, ddddD=Sd, and mmmmM=Sm.
+  constexpr IValueT VmovssOpcode = B23 | B21 | B20 | B6;
+  constexpr IValueT S0 = 0;
+  emitVFPsss(Cond, VmovssOpcode, Sd, S0, Sm);
+}
+
 void AssemblerARM32::emitMulOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd,
                                IValueT Rn, IValueT Rm, IValueT Rs,
                                bool SetFlags) {
   assert(Rd < RegARM32::getNumGPRegs());
   assert(Rn < RegARM32::getNumGPRegs());
   assert(Rm < RegARM32::getNumGPRegs());
   assert(Rs < RegARM32::getNumGPRegs());
   assert(CondARM32::isDefined(Cond));
   IValueT Encoding = Opcode | (encodeCondition(Cond) << kConditionShift) |
                      (encodeBool(SetFlags) << kSShift) | (Rn << kRnShift) |
@@ skipping 1624 matching lines @@
   assert(Rt2 != RegARM32::Encoded_Reg_pc);
   assert(Rt != Rt2);
   assert(CondARM32::isDefined(Cond));
   IValueT Encoding = B27 | B26 | B22 | B11 | B9 | B8 | B4 |
                      (encodeCondition(Cond) << kConditionShift) | (Rt2 << 16) |
                      (Rt << 12) | (getYInRegYXXXX(Dm) << 5) |
                      getXXXXInRegYXXXX(Dm);
   emitInst(Encoding);
 }
 
+void AssemblerARM32::vmovqir(const Operand *OpQn, uint32_t Index,
+                             const Operand *OpRt, CondARM32::Cond Cond) {
+  // VMOV (ARM core register to scalar) - ARM section A8.8.341, encoding A1:
+  //   vmov<c>.<size> <Dn[x]>, <Rt>
+  constexpr const char *Vmovdr = "vmovdr";
+  constexpr bool IsExtract = true;
+  emitInsertExtractInt(Cond, OpQn, Index, OpRt, !IsExtract, Vmovdr);
+}
+
+void AssemblerARM32::vmovqis(const Operand *OpQd, uint32_t Index,
+                             const Operand *OpSm, CondARM32::Cond Cond) {
+  constexpr const char *Vmovqis = "vmovqis";
+  assert(Index < 4);
+  IValueT Sd = mapQRegToSReg(encodeQRegister(OpQd, "Qd", Vmovqis)) + Index;
+  IValueT Sm = encodeSRegister(OpSm, "Sm", Vmovqis);
+  emitMoveSS(Cond, Sd, Sm);
+}
+
+void AssemblerARM32::vmovrqi(const Operand *OpRt, const Operand *OpQn,
+                             uint32_t Index, CondARM32::Cond Cond) {
+  // VMOV (scalar to ARM core register) - ARM section A8.8.342, encoding A1:
+  //   vmov<c>.<dt> <Rt>, <Dn[x]>
+  constexpr const char *Vmovrd = "vmovrd";
+  constexpr bool IsExtract = true;
+  emitInsertExtractInt(Cond, OpQn, Index, OpRt, IsExtract, Vmovrd);
+}
+
 void AssemblerARM32::vmovrrd(const Operand *OpRt, const Operand *OpRt2,
                              const Operand *OpDm, CondARM32::Cond Cond) {
   // VMOV (between two ARM core registers and a doubleword extension register).
   // ARM section A8.8.345, encoding A1:
   //   vmov<c> <Rt>, <Rt2>, <Dm>
   //
   // cccc11000101xxxxyyyy101100M1mmmm where cccc=Cond, xxxx=Rt, yyyy=Rt2, and
   // Mmmmm=Dm.
   constexpr const char *Vmovrrd = "vmovrrd";
   IValueT Rt = encodeGPRegister(OpRt, "Rt", Vmovrrd);
@@ skipping 42 matching lines @@
   IValueT Imm8 = OpFpImm->getModifiedImm();
   assert(Imm8 < (1 << 8));
   constexpr IValueT VmovsOpcode = B23 | B21 | B20;
   IValueT OpcodePlusImm8 = VmovsOpcode | ((Imm8 >> 4) << 16) | (Imm8 & 0xf);
   constexpr IValueT S0 = 0;
   emitVFPsss(Cond, OpcodePlusImm8, Sd, S0, S0);
 }
 
 void AssemblerARM32::vmovss(const Operand *OpSd, const Variable *OpSm,
                             CondARM32::Cond Cond) {
-  // VMOV (register) - ARM section A8.8.340, encoding A2:
-  //   vmov<c>.f32 <Sd>, <Sm>
-  //
-  // cccc11101D110000dddd101001M0mmmm where cccc=Cond, ddddD=Sd, and mmmmM=Sm.
   constexpr const char *Vmovss = "Vmovss";
   IValueT Sd = encodeSRegister(OpSd, "Sd", Vmovss);
   IValueT Sm = encodeSRegister(OpSm, "Sm", Vmovss);
-  constexpr IValueT VmovssOpcode = B23 | B21 | B20 | B6;
-  constexpr IValueT S0 = 0;
-  emitVFPsss(Cond, VmovssOpcode, Sd, S0, Sm);
+  emitMoveSS(Cond, Sd, Sm);
+}
+
+void AssemblerARM32::vmovsqi(const Operand *OpSd, const Operand *OpQm,
+                             uint32_t Index, CondARM32::Cond Cond) {
+  constexpr const char *Vmovsqi = "vmovsqi";
+  IValueT Sd = encodeSRegister(OpSd, "Sd", Vmovsqi);

[John, 2016/02/10 20:25:38]

const

[Karl, 2016/02/10 21:31:03]

Done.

+  assert(Index < 4);
+  IValueT Sm = mapQRegToSReg(encodeQRegister(OpQm, "Qm", Vmovsqi)) + Index;

[John, 2016/02/10 20:25:38]

const

[Karl, 2016/02/10 21:31:02]

Done.

+  emitMoveSS(Cond, Sd, Sm);
 }
 
 void AssemblerARM32::vmovsr(const Operand *OpSn, const Operand *OpRt,
                             CondARM32::Cond Cond) {
   // VMOV (between ARM core register and single-precision register)
   //   ARM section A8.8.343, encoding A1.
   //
   //   vmov<c> <Sn>, <Rt>
   //
   // cccc11100000nnnntttt1010N0010000 where cccc=Cond, nnnnN = Sn, and tttt=Rt.
@@ skipping 311 matching lines @@
   constexpr const char *Vsqrts = "vsqrts";
   IValueT Sd = encodeSRegister(OpSd, "Sd", Vsqrts);
   IValueT Sm = encodeSRegister(OpSm, "Sm", Vsqrts);
   constexpr IValueT VsqrtsOpcode = B23 | B21 | B20 | B16 | B7 | B6;
   constexpr IValueT S0 = 0;
   emitVFPsss(Cond, VsqrtsOpcode, Sd, S0, Sm);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice