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| 1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===// | 1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 /// | 9 /// |
| 10 /// \file | 10 /// \file |
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| 756 void _udiv(Variable *Dest, Variable *Src0, Variable *Src1, | 756 void _udiv(Variable *Dest, Variable *Src0, Variable *Src1, |
| 757 CondARM32::Cond Pred = CondARM32::AL) { | 757 CondARM32::Cond Pred = CondARM32::AL) { |
| 758 Context.insert<InstARM32Udiv>(Dest, Src0, Src1, Pred); | 758 Context.insert<InstARM32Udiv>(Dest, Src0, Src1, Pred); |
| 759 } | 759 } |
| 760 void _umull(Variable *DestLo, Variable *DestHi, Variable *Src0, | 760 void _umull(Variable *DestLo, Variable *DestHi, Variable *Src0, |
| 761 Variable *Src1, CondARM32::Cond Pred = CondARM32::AL) { | 761 Variable *Src1, CondARM32::Cond Pred = CondARM32::AL) { |
| 762 Context.insert<InstARM32Umull>(DestLo, DestHi, Src0, Src1, Pred); | 762 Context.insert<InstARM32Umull>(DestLo, DestHi, Src0, Src1, Pred); |
| 763 // Model the modification to the second dest as a fake def. Note that the | 763 // Model the modification to the second dest as a fake def. Note that the |
| 764 // def is not predicated. | 764 // def is not predicated. |
| 765 Context.insert<InstFakeDef>(DestHi, DestLo); | 765 Context.insert<InstFakeDef>(DestHi, DestLo); |
| 766 Context.insert<InstFakeUse>(DestHi); |
| 766 } | 767 } |
| 767 void _uxt(Variable *Dest, Variable *Src0, | 768 void _uxt(Variable *Dest, Variable *Src0, |
| 768 CondARM32::Cond Pred = CondARM32::AL) { | 769 CondARM32::Cond Pred = CondARM32::AL) { |
| 769 Context.insert<InstARM32Uxt>(Dest, Src0, Pred); | 770 Context.insert<InstARM32Uxt>(Dest, Src0, Pred); |
| 770 } | 771 } |
| 771 void _vabs(Variable *Dest, Variable *Src, | 772 void _vabs(Variable *Dest, Variable *Src, |
| 772 CondARM32::Cond Pred = CondARM32::AL) { | 773 CondARM32::Cond Pred = CondARM32::AL) { |
| 773 Context.insert<InstARM32Vabs>(Dest, Src, Pred); | 774 Context.insert<InstARM32Vabs>(Dest, Src, Pred); |
| 774 } | 775 } |
| 775 void _vadd(Variable *Dest, Variable *Src0, Variable *Src1) { | 776 void _vadd(Variable *Dest, Variable *Src0, Variable *Src1) { |
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| 1216 private: | 1217 private: |
| 1217 ~TargetHeaderARM32() = default; | 1218 ~TargetHeaderARM32() = default; |
| 1218 | 1219 |
| 1219 TargetARM32Features CPUFeatures; | 1220 TargetARM32Features CPUFeatures; |
| 1220 }; | 1221 }; |
| 1221 | 1222 |
| 1222 } // end of namespace ARM32 | 1223 } // end of namespace ARM32 |
| 1223 } // end of namespace Ice | 1224 } // end of namespace Ice |
| 1224 | 1225 |
| 1225 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H | 1226 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H |
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