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1 ; Show that we know how to translate rsb. Uses shl as example, because it | 1 ; Show that we know how to translate rsb. Uses shl as example, because it |
2 ; uses rsb for type i64. | 2 ; uses rsb for type i64. |
3 | 3 |
4 ; Also shows an example of a register-shifted register (data) operation. | 4 ; Also shows an example of a register-shifted register (data) operation. |
5 | 5 |
6 ; REQUIRES: allow_dump | 6 ; REQUIRES: allow_dump |
7 | 7 |
8 ; Compile using standalone assembler. | 8 ; Compile using standalone assembler. |
9 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \ | 9 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \ |
10 ; RUN: | FileCheck %s --check-prefix=ASM | 10 ; RUN: | FileCheck %s --check-prefix=ASM |
11 | 11 |
12 ; Show bytes in assembled standalone code. | 12 ; Show bytes in assembled standalone code. |
13 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \ | 13 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \ |
14 ; RUN: --args -Om1 | FileCheck %s --check-prefix=DIS | 14 ; RUN: --args -Om1 | FileCheck %s --check-prefix=DIS |
15 | 15 |
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31 ; IASM-NEXT:.LshiftLeft$entry: | 31 ; IASM-NEXT:.LshiftLeft$entry: |
32 | 32 |
33 ; ASM-NEXT: sub sp, sp, #24 | 33 ; ASM-NEXT: sub sp, sp, #24 |
34 ; DIS-NEXT: 0: e24dd018 | 34 ; DIS-NEXT: 0: e24dd018 |
35 ; IASM-NEXT: .byte 0x18 | 35 ; IASM-NEXT: .byte 0x18 |
36 ; IASM-NEXT: .byte 0xd0 | 36 ; IASM-NEXT: .byte 0xd0 |
37 ; IASM-NEXT: .byte 0x4d | 37 ; IASM-NEXT: .byte 0x4d |
38 ; IASM-NEXT: .byte 0xe2 | 38 ; IASM-NEXT: .byte 0xe2 |
39 | 39 |
40 ; ASM-NEXT: str r0, [sp, #20] | 40 ; ASM-NEXT: str r0, [sp, #20] |
41 ; ASM-NEXT: # [sp, #20] = def.pseudo | 41 ; ASM-NEXT: # [sp, #20] = def.pseudo |
42 ; DIS-NEXT: 4: e58d0014 | 42 ; DIS-NEXT: 4: e58d0014 |
43 ; IASM-NEXT: .byte 0x14 | 43 ; IASM-NEXT: .byte 0x14 |
44 ; IASM-NEXT: .byte 0x0 | 44 ; IASM-NEXT: .byte 0x0 |
45 ; IASM-NEXT: .byte 0x8d | 45 ; IASM-NEXT: .byte 0x8d |
46 ; IASM-NEXT: .byte 0xe5 | 46 ; IASM-NEXT: .byte 0xe5 |
47 | 47 |
48 ; ASM-NEXT: mov r0, r1 | 48 ; ASM-NEXT: mov r0, r1 |
49 ; DIS-NEXT: 8: e1a00001 | 49 ; DIS-NEXT: 8: e1a00001 |
50 ; IASM-NEXT: .byte 0x1 | 50 ; IASM-NEXT: .byte 0x1 |
51 ; IASM-NEXT: .byte 0x0 | 51 ; IASM-NEXT: .byte 0x0 |
52 ; IASM-NEXT: .byte 0xa0 | 52 ; IASM-NEXT: .byte 0xa0 |
53 ; IASM-NEXT: .byte 0xe1 | 53 ; IASM-NEXT: .byte 0xe1 |
54 | 54 |
55 ; ASM-NEXT: str r0, [sp, #16] | 55 ; ASM-NEXT: str r0, [sp, #16] |
56 ; ASM-NEXT: # [sp, #16] = def.pseudo | 56 ; ASM-NEXT: # [sp, #16] = def.pseudo |
57 ; DIS-NEXT: c: e58d0010 | 57 ; DIS-NEXT: c: e58d0010 |
58 ; IASM-NEXT: .byte 0x10 | 58 ; IASM-NEXT: .byte 0x10 |
59 ; IASM-NEXT: .byte 0x0 | 59 ; IASM-NEXT: .byte 0x0 |
60 ; IASM-NEXT: .byte 0x8d | 60 ; IASM-NEXT: .byte 0x8d |
61 ; IASM-NEXT: .byte 0xe5 | 61 ; IASM-NEXT: .byte 0xe5 |
62 | 62 |
63 ; ASM-NEXT: mov r0, r2 | 63 ; ASM-NEXT: mov r0, r2 |
64 ; DIS-NEXT: 10: e1a00002 | 64 ; DIS-NEXT: 10: e1a00002 |
65 ; IASM-NEXT: .byte 0x2 | 65 ; IASM-NEXT: .byte 0x2 |
66 ; IASM-NEXT: .byte 0x0 | 66 ; IASM-NEXT: .byte 0x0 |
67 ; IASM-NEXT: .byte 0xa0 | 67 ; IASM-NEXT: .byte 0xa0 |
68 ; IASM-NEXT: .byte 0xe1 | 68 ; IASM-NEXT: .byte 0xe1 |
69 | 69 |
70 ; ASM-NEXT: str r0, [sp, #12] | 70 ; ASM-NEXT: str r0, [sp, #12] |
71 ; ASM-NEXT: # [sp, #12] = def.pseudo | 71 ; ASM-NEXT: # [sp, #12] = def.pseudo |
72 ; DIS-NEXT: 14: e58d000c | 72 ; DIS-NEXT: 14: e58d000c |
73 ; IASM-NEXT: .byte 0xc | 73 ; IASM-NEXT: .byte 0xc |
74 ; IASM-NEXT: .byte 0x0 | 74 ; IASM-NEXT: .byte 0x0 |
75 ; IASM-NEXT: .byte 0x8d | 75 ; IASM-NEXT: .byte 0x8d |
76 ; IASM-NEXT: .byte 0xe5 | 76 ; IASM-NEXT: .byte 0xe5 |
77 | 77 |
78 ; ASM-NEXT: mov r0, r3 | 78 ; ASM-NEXT: mov r0, r3 |
79 ; DIS-NEXT: 18: e1a00003 | 79 ; DIS-NEXT: 18: e1a00003 |
80 ; IASM-NEXT: .byte 0x3 | 80 ; IASM-NEXT: .byte 0x3 |
81 ; IASM-NEXT: .byte 0x0 | 81 ; IASM-NEXT: .byte 0x0 |
82 ; IASM-NEXT: .byte 0xa0 | 82 ; IASM-NEXT: .byte 0xa0 |
83 ; IASM-NEXT: .byte 0xe1 | 83 ; IASM-NEXT: .byte 0xe1 |
84 | 84 |
85 ; ASM-NEXT: str r0, [sp, #8] | 85 ; ASM-NEXT: str r0, [sp, #8] |
86 ; ASM-NEXT: # [sp, #8] = def.pseudo | 86 ; ASM-NEXT: # [sp, #8] = def.pseudo |
87 ; DIS-NEXT: 1c: e58d0008 | 87 ; DIS-NEXT: 1c: e58d0008 |
88 ; IASM-NEXT: .byte 0x8 | 88 ; IASM-NEXT: .byte 0x8 |
89 ; IASM-NEXT: .byte 0x0 | 89 ; IASM-NEXT: .byte 0x0 |
90 ; IASM-NEXT: .byte 0x8d | 90 ; IASM-NEXT: .byte 0x8d |
91 ; IASM-NEXT: .byte 0xe5 | 91 ; IASM-NEXT: .byte 0xe5 |
92 | 92 |
93 %result = shl i64 %v, %l | 93 %result = shl i64 %v, %l |
94 | 94 |
95 ; ASM-NEXT: ldr r0, [sp, #20] | 95 ; ASM-NEXT: ldr r0, [sp, #20] |
96 ; DIS-NEXT: 20: e59d0014 | 96 ; DIS-NEXT: 20: e59d0014 |
(...skipping 34 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
131 ; ***** Here is an example of a register-shifted register ***** | 131 ; ***** Here is an example of a register-shifted register ***** |
132 ; ASM-NEXT: orr r1, r3, r1, lsl r2 | 132 ; ASM-NEXT: orr r1, r3, r1, lsl r2 |
133 ; DIS-NEXT: 34: e1831211 | 133 ; DIS-NEXT: 34: e1831211 |
134 ; IASM-NEXT: .byte 0x11 | 134 ; IASM-NEXT: .byte 0x11 |
135 ; IASM-NEXT: .byte 0x12 | 135 ; IASM-NEXT: .byte 0x12 |
136 ; IASM-NEXT: .byte 0x83 | 136 ; IASM-NEXT: .byte 0x83 |
137 ; IASM-NEXT: .byte 0xe1 | 137 ; IASM-NEXT: .byte 0xe1 |
138 | 138 |
139 ret i64 %result | 139 ret i64 %result |
140 } | 140 } |
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