tests_lit/assembler/arm32/dmb.ll - Issue 1678133003: Subzero: Fix trailing whitespace errors.

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Side by Side Diff: tests_lit/assembler/arm32/dmb.ll

Issue 1678133003: Subzero: Fix trailing whitespace errors. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master

Patch Set: Rebase Created 4 years, 10 months ago

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1 ; Show that we know how to encode the dmb instruction.	1 ; Show that we know how to encode the dmb instruction.

2	2

3 ; REQUIRES: allow_dump	3 ; REQUIRES: allow_dump

4	4

5 ; Compile using standalone assembler.	5 ; Compile using standalone assembler.

6 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \	6 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \

7 ; RUN: \| FileCheck %s --check-prefix=ASM	7 ; RUN: \| FileCheck %s --check-prefix=ASM

8	8

9 ; Show bytes in assembled standalone code.	9 ; Show bytes in assembled standalone code.

10 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \	10 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \

(...skipping 19 matching lines...) Expand all Loading...
30 ; IASM-NEXT:.Ltest_atomic_load_8$entry:	30 ; IASM-NEXT:.Ltest_atomic_load_8$entry:

31	31

32 ; ASM-NEXT: sub sp, sp, #12	32 ; ASM-NEXT: sub sp, sp, #12

33 ; DIS-NEXT: 0: e24dd00c	33 ; DIS-NEXT: 0: e24dd00c

34 ; IASM-NEXT: .byte 0xc	34 ; IASM-NEXT: .byte 0xc

35 ; IASM-NEXT: .byte 0xd0	35 ; IASM-NEXT: .byte 0xd0

36 ; IASM-NEXT: .byte 0x4d	36 ; IASM-NEXT: .byte 0x4d

37 ; IASM-NEXT: .byte 0xe2	37 ; IASM-NEXT: .byte 0xe2

38	38

39 ; ASM-NEXT: str r0, [sp, #8]	39 ; ASM-NEXT: str r0, [sp, #8]

40 ; ASM-NEXT:» # [sp, #8] = def.pseudo	40 ; ASM-NEXT:» # [sp, #8] = def.pseudo

41 ; DIS-NEXT: 4: e58d0008	41 ; DIS-NEXT: 4: e58d0008

42 ; IASM-NEXT: .byte 0x8	42 ; IASM-NEXT: .byte 0x8

43 ; IASM-NEXT: .byte 0x0	43 ; IASM-NEXT: .byte 0x0

44 ; IASM-NEXT: .byte 0x8d	44 ; IASM-NEXT: .byte 0x8d

45 ; IASM-NEXT: .byte 0xe5	45 ; IASM-NEXT: .byte 0xe5

46	46

47 %ptr = inttoptr i32 %iptr to i8*	47 %ptr = inttoptr i32 %iptr to i8*

48 ; parameter value "6" is for the sequential consistency memory order.	48 ; parameter value "6" is for the sequential consistency memory order.

49 %i = call i8 @llvm.nacl.atomic.load.i8(i8* %ptr, i32 6)	49 %i = call i8 @llvm.nacl.atomic.load.i8(i8* %ptr, i32 6)

50	50

(...skipping 14 matching lines...) Expand all Loading...
65 ; ASM-NEXT: dmb sy	65 ; ASM-NEXT: dmb sy

66 ; DIS-NEXT: 10: f57ff05f	66 ; DIS-NEXT: 10: f57ff05f

67 ; IASM-NEXT: .byte 0x5f	67 ; IASM-NEXT: .byte 0x5f

68 ; IASM-NEXT: .byte 0xf0	68 ; IASM-NEXT: .byte 0xf0

69 ; IASM-NEXT: .byte 0x7f	69 ; IASM-NEXT: .byte 0x7f

70 ; IASM-NEXT: .byte 0xf5	70 ; IASM-NEXT: .byte 0xf5

71	71

72 %r = zext i8 %i to i32	72 %r = zext i8 %i to i32

73 ret i32 %r	73 ret i32 %r

74 }	74 }

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