pydir/gen_arm32_reg_tables.py - Issue 1678133003: Subzero: Fix trailing whitespace errors.

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Side by Side Diff: pydir/gen_arm32_reg_tables.py

Issue 1678133003: Subzero: Fix trailing whitespace errors. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master

Patch Set: Rebase Created 4 years, 10 months ago

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1 import os	1 import os

2 import sys	2 import sys

3	3

4 class RegAliases(object):	4 class RegAliases(object):

5 def __init__(self, AliasesStr):	5 def __init__(self, AliasesStr):

6 self.Aliases = list(Alias.strip() for Alias in AliasesStr.split(','))	6 self.Aliases = list(Alias.strip() for Alias in AliasesStr.split(','))

7	7

8 def __str__(self):	8 def __str__(self):

9 return 'REGLIST{AliasCount}(RegARM32, {Aliases})'.format(	9 return 'REGLIST{AliasCount}(RegARM32, {Aliases})'.format(

10 AliasCount=len(self.Aliases), Aliases=', '.join(self.Aliases))	10 AliasCount=len(self.Aliases), Aliases=', '.join(self.Aliases))

(...skipping 203 matching lines...) Expand 10 before \| Expand all \| Expand 10 after Loading...
214 assert (AllRegs[Alias].Features.LivesInVFP() ==	214 assert (AllRegs[Alias].Features.LivesInVFP() ==

215 Reg.Features.LivesInVFP()), '%s VS %s' % (Reg, AllRegs[Alias])	215 Reg.Features.LivesInVFP()), '%s VS %s' % (Reg, AllRegs[Alias])

216	216

217 print ("// This file was auto generated by the {script} script.\n"	217 print ("// This file was auto generated by the {script} script.\n"

218 "// Do not modify it: modify the script instead.\n"	218 "// Do not modify it: modify the script instead.\n"

219 "\n"	219 "\n"

220 "#ifndef SUBZERO_SRC_ICEREGISTERSARM32_DEF\n"	220 "#ifndef SUBZERO_SRC_ICEREGISTERSARM32_DEF\n"

221 "#define SUBZERO_SRC_ICEREGISTERSARM32_DEF\n".format(script=os.path.basen ame(sys.argv[0])))	221 "#define SUBZERO_SRC_ICEREGISTERSARM32_DEF\n".format(script=os.path.basen ame(sys.argv[0])))

222	222

223 for Name, RegClass in RegClasses:	223 for Name, RegClass in RegClasses:

224 print '\n//{xmacro}'.format(xmacro=Reg.DefiningXMacro())	224 print '//{xmacro}'.format(xmacro=Reg.DefiningXMacro())

225 print "#define REGARM32_%s_TABLE" % Name,	225 print "#define REGARM32_%s_TABLE" % Name,

226 for Reg in RegClass:	226 for Reg in RegClass:

227 print '\\\n X({Reg})'.format(Reg=Reg),	227 sys.stdout.write(' \\\n X({Reg})'.format(Reg=Reg))

228 print '\n'	228 print '\n'

229 print "#endif // SUBZERO_SRC_ICEREGISTERSARM32_DEF",	229 print "#endif // SUBZERO_SRC_ICEREGISTERSARM32_DEF",

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