OLD | NEW |
1 /* | 1 /* |
2 * Copyright 2011 The LibYuv Project Authors. All rights reserved. | 2 * Copyright 2011 The LibYuv Project Authors. All rights reserved. |
3 * | 3 * |
4 * Use of this source code is governed by a BSD-style license | 4 * Use of this source code is governed by a BSD-style license |
5 * that can be found in the LICENSE file in the root of the source | 5 * that can be found in the LICENSE file in the root of the source |
6 * tree. An additional intellectual property rights grant can be found | 6 * tree. An additional intellectual property rights grant can be found |
7 * in the file PATENTS. All contributing project authors may | 7 * in the file PATENTS. All contributing project authors may |
8 * be found in the AUTHORS file in the root of the source tree. | 8 * be found in the AUTHORS file in the root of the source tree. |
9 */ | 9 */ |
10 | 10 |
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78 ScaleRowDown2 = filtering == kFilterNone ? ScaleRowDown2_Any_AVX2 : | 78 ScaleRowDown2 = filtering == kFilterNone ? ScaleRowDown2_Any_AVX2 : |
79 (filtering == kFilterLinear ? ScaleRowDown2Linear_Any_AVX2 : | 79 (filtering == kFilterLinear ? ScaleRowDown2Linear_Any_AVX2 : |
80 ScaleRowDown2Box_Any_AVX2); | 80 ScaleRowDown2Box_Any_AVX2); |
81 if (IS_ALIGNED(dst_width, 32)) { | 81 if (IS_ALIGNED(dst_width, 32)) { |
82 ScaleRowDown2 = filtering == kFilterNone ? ScaleRowDown2_AVX2 : | 82 ScaleRowDown2 = filtering == kFilterNone ? ScaleRowDown2_AVX2 : |
83 (filtering == kFilterLinear ? ScaleRowDown2Linear_AVX2 : | 83 (filtering == kFilterLinear ? ScaleRowDown2Linear_AVX2 : |
84 ScaleRowDown2Box_AVX2); | 84 ScaleRowDown2Box_AVX2); |
85 } | 85 } |
86 } | 86 } |
87 #endif | 87 #endif |
88 #if defined(HAS_SCALEROWDOWN2_MIPS_DSPR2) | 88 #if defined(HAS_SCALEROWDOWN2_DSPR2) |
89 if (TestCpuFlag(kCpuHasMIPS_DSPR2) && IS_ALIGNED(src_ptr, 4) && | 89 if (TestCpuFlag(kCpuHasDSPR2) && IS_ALIGNED(src_ptr, 4) && |
90 IS_ALIGNED(src_stride, 4) && IS_ALIGNED(row_stride, 4) && | 90 IS_ALIGNED(src_stride, 4) && IS_ALIGNED(row_stride, 4) && |
91 IS_ALIGNED(dst_ptr, 4) && IS_ALIGNED(dst_stride, 4)) { | 91 IS_ALIGNED(dst_ptr, 4) && IS_ALIGNED(dst_stride, 4)) { |
92 ScaleRowDown2 = filtering ? | 92 ScaleRowDown2 = filtering ? |
93 ScaleRowDown2Box_MIPS_DSPR2 : ScaleRowDown2_MIPS_DSPR2; | 93 ScaleRowDown2Box_DSPR2 : ScaleRowDown2_DSPR2; |
94 } | 94 } |
95 #endif | 95 #endif |
96 | 96 |
97 if (filtering == kFilterLinear) { | 97 if (filtering == kFilterLinear) { |
98 src_stride = 0; | 98 src_stride = 0; |
99 } | 99 } |
100 // TODO(fbarchard): Loop through source height to allow odd height. | 100 // TODO(fbarchard): Loop through source height to allow odd height. |
101 for (y = 0; y < dst_height; ++y) { | 101 for (y = 0; y < dst_height; ++y) { |
102 ScaleRowDown2(src_ptr, src_stride, dst_ptr, dst_width); | 102 ScaleRowDown2(src_ptr, src_stride, dst_ptr, dst_width); |
103 src_ptr += row_stride; | 103 src_ptr += row_stride; |
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128 ScaleRowDown2_16_NEON; | 128 ScaleRowDown2_16_NEON; |
129 } | 129 } |
130 #endif | 130 #endif |
131 #if defined(HAS_SCALEROWDOWN2_16_SSE2) | 131 #if defined(HAS_SCALEROWDOWN2_16_SSE2) |
132 if (TestCpuFlag(kCpuHasSSE2) && IS_ALIGNED(dst_width, 16)) { | 132 if (TestCpuFlag(kCpuHasSSE2) && IS_ALIGNED(dst_width, 16)) { |
133 ScaleRowDown2 = filtering == kFilterNone ? ScaleRowDown2_16_SSE2 : | 133 ScaleRowDown2 = filtering == kFilterNone ? ScaleRowDown2_16_SSE2 : |
134 (filtering == kFilterLinear ? ScaleRowDown2Linear_16_SSE2 : | 134 (filtering == kFilterLinear ? ScaleRowDown2Linear_16_SSE2 : |
135 ScaleRowDown2Box_16_SSE2); | 135 ScaleRowDown2Box_16_SSE2); |
136 } | 136 } |
137 #endif | 137 #endif |
138 #if defined(HAS_SCALEROWDOWN2_16_MIPS_DSPR2) | 138 #if defined(HAS_SCALEROWDOWN2_16_DSPR2) |
139 if (TestCpuFlag(kCpuHasMIPS_DSPR2) && IS_ALIGNED(src_ptr, 4) && | 139 if (TestCpuFlag(kCpuHasDSPR2) && IS_ALIGNED(src_ptr, 4) && |
140 IS_ALIGNED(src_stride, 4) && IS_ALIGNED(row_stride, 4) && | 140 IS_ALIGNED(src_stride, 4) && IS_ALIGNED(row_stride, 4) && |
141 IS_ALIGNED(dst_ptr, 4) && IS_ALIGNED(dst_stride, 4)) { | 141 IS_ALIGNED(dst_ptr, 4) && IS_ALIGNED(dst_stride, 4)) { |
142 ScaleRowDown2 = filtering ? | 142 ScaleRowDown2 = filtering ? |
143 ScaleRowDown2Box_16_MIPS_DSPR2 : ScaleRowDown2_16_MIPS_DSPR2; | 143 ScaleRowDown2Box_16_DSPR2 : ScaleRowDown2_16_DSPR2; |
144 } | 144 } |
145 #endif | 145 #endif |
146 | 146 |
147 if (filtering == kFilterLinear) { | 147 if (filtering == kFilterLinear) { |
148 src_stride = 0; | 148 src_stride = 0; |
149 } | 149 } |
150 // TODO(fbarchard): Loop through source height to allow odd height. | 150 // TODO(fbarchard): Loop through source height to allow odd height. |
151 for (y = 0; y < dst_height; ++y) { | 151 for (y = 0; y < dst_height; ++y) { |
152 ScaleRowDown2(src_ptr, src_stride, dst_ptr, dst_width); | 152 ScaleRowDown2(src_ptr, src_stride, dst_ptr, dst_width); |
153 src_ptr += row_stride; | 153 src_ptr += row_stride; |
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193 #endif | 193 #endif |
194 #if defined(HAS_SCALEROWDOWN4_AVX2) | 194 #if defined(HAS_SCALEROWDOWN4_AVX2) |
195 if (TestCpuFlag(kCpuHasAVX2)) { | 195 if (TestCpuFlag(kCpuHasAVX2)) { |
196 ScaleRowDown4 = filtering ? | 196 ScaleRowDown4 = filtering ? |
197 ScaleRowDown4Box_Any_AVX2 : ScaleRowDown4_Any_AVX2; | 197 ScaleRowDown4Box_Any_AVX2 : ScaleRowDown4_Any_AVX2; |
198 if (IS_ALIGNED(dst_width, 16)) { | 198 if (IS_ALIGNED(dst_width, 16)) { |
199 ScaleRowDown4 = filtering ? ScaleRowDown4Box_AVX2 : ScaleRowDown4_AVX2; | 199 ScaleRowDown4 = filtering ? ScaleRowDown4Box_AVX2 : ScaleRowDown4_AVX2; |
200 } | 200 } |
201 } | 201 } |
202 #endif | 202 #endif |
203 #if defined(HAS_SCALEROWDOWN4_MIPS_DSPR2) | 203 #if defined(HAS_SCALEROWDOWN4_DSPR2) |
204 if (TestCpuFlag(kCpuHasMIPS_DSPR2) && IS_ALIGNED(row_stride, 4) && | 204 if (TestCpuFlag(kCpuHasDSPR2) && IS_ALIGNED(row_stride, 4) && |
205 IS_ALIGNED(src_ptr, 4) && IS_ALIGNED(src_stride, 4) && | 205 IS_ALIGNED(src_ptr, 4) && IS_ALIGNED(src_stride, 4) && |
206 IS_ALIGNED(dst_ptr, 4) && IS_ALIGNED(dst_stride, 4)) { | 206 IS_ALIGNED(dst_ptr, 4) && IS_ALIGNED(dst_stride, 4)) { |
207 ScaleRowDown4 = filtering ? | 207 ScaleRowDown4 = filtering ? |
208 ScaleRowDown4Box_MIPS_DSPR2 : ScaleRowDown4_MIPS_DSPR2; | 208 ScaleRowDown4Box_DSPR2 : ScaleRowDown4_DSPR2; |
209 } | 209 } |
210 #endif | 210 #endif |
211 | 211 |
212 if (filtering == kFilterLinear) { | 212 if (filtering == kFilterLinear) { |
213 src_stride = 0; | 213 src_stride = 0; |
214 } | 214 } |
215 for (y = 0; y < dst_height; ++y) { | 215 for (y = 0; y < dst_height; ++y) { |
216 ScaleRowDown4(src_ptr, src_stride, dst_ptr, dst_width); | 216 ScaleRowDown4(src_ptr, src_stride, dst_ptr, dst_width); |
217 src_ptr += row_stride; | 217 src_ptr += row_stride; |
218 dst_ptr += dst_stride; | 218 dst_ptr += dst_stride; |
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238 ScaleRowDown4 = filtering ? ScaleRowDown4Box_16_NEON : | 238 ScaleRowDown4 = filtering ? ScaleRowDown4Box_16_NEON : |
239 ScaleRowDown4_16_NEON; | 239 ScaleRowDown4_16_NEON; |
240 } | 240 } |
241 #endif | 241 #endif |
242 #if defined(HAS_SCALEROWDOWN4_16_SSE2) | 242 #if defined(HAS_SCALEROWDOWN4_16_SSE2) |
243 if (TestCpuFlag(kCpuHasSSE2) && IS_ALIGNED(dst_width, 8)) { | 243 if (TestCpuFlag(kCpuHasSSE2) && IS_ALIGNED(dst_width, 8)) { |
244 ScaleRowDown4 = filtering ? ScaleRowDown4Box_16_SSE2 : | 244 ScaleRowDown4 = filtering ? ScaleRowDown4Box_16_SSE2 : |
245 ScaleRowDown4_16_SSE2; | 245 ScaleRowDown4_16_SSE2; |
246 } | 246 } |
247 #endif | 247 #endif |
248 #if defined(HAS_SCALEROWDOWN4_16_MIPS_DSPR2) | 248 #if defined(HAS_SCALEROWDOWN4_16_DSPR2) |
249 if (TestCpuFlag(kCpuHasMIPS_DSPR2) && IS_ALIGNED(row_stride, 4) && | 249 if (TestCpuFlag(kCpuHasDSPR2) && IS_ALIGNED(row_stride, 4) && |
250 IS_ALIGNED(src_ptr, 4) && IS_ALIGNED(src_stride, 4) && | 250 IS_ALIGNED(src_ptr, 4) && IS_ALIGNED(src_stride, 4) && |
251 IS_ALIGNED(dst_ptr, 4) && IS_ALIGNED(dst_stride, 4)) { | 251 IS_ALIGNED(dst_ptr, 4) && IS_ALIGNED(dst_stride, 4)) { |
252 ScaleRowDown4 = filtering ? | 252 ScaleRowDown4 = filtering ? |
253 ScaleRowDown4Box_16_MIPS_DSPR2 : ScaleRowDown4_16_MIPS_DSPR2; | 253 ScaleRowDown4Box_16_DSPR2 : ScaleRowDown4_16_DSPR2; |
254 } | 254 } |
255 #endif | 255 #endif |
256 | 256 |
257 if (filtering == kFilterLinear) { | 257 if (filtering == kFilterLinear) { |
258 src_stride = 0; | 258 src_stride = 0; |
259 } | 259 } |
260 for (y = 0; y < dst_height; ++y) { | 260 for (y = 0; y < dst_height; ++y) { |
261 ScaleRowDown4(src_ptr, src_stride, dst_ptr, dst_width); | 261 ScaleRowDown4(src_ptr, src_stride, dst_ptr, dst_width); |
262 src_ptr += row_stride; | 262 src_ptr += row_stride; |
263 dst_ptr += dst_stride; | 263 dst_ptr += dst_stride; |
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318 if (!filtering) { | 318 if (!filtering) { |
319 ScaleRowDown34_0 = ScaleRowDown34_SSSE3; | 319 ScaleRowDown34_0 = ScaleRowDown34_SSSE3; |
320 ScaleRowDown34_1 = ScaleRowDown34_SSSE3; | 320 ScaleRowDown34_1 = ScaleRowDown34_SSSE3; |
321 } else { | 321 } else { |
322 ScaleRowDown34_0 = ScaleRowDown34_0_Box_SSSE3; | 322 ScaleRowDown34_0 = ScaleRowDown34_0_Box_SSSE3; |
323 ScaleRowDown34_1 = ScaleRowDown34_1_Box_SSSE3; | 323 ScaleRowDown34_1 = ScaleRowDown34_1_Box_SSSE3; |
324 } | 324 } |
325 } | 325 } |
326 } | 326 } |
327 #endif | 327 #endif |
328 #if defined(HAS_SCALEROWDOWN34_MIPS_DSPR2) | 328 #if defined(HAS_SCALEROWDOWN34_DSPR2) |
329 if (TestCpuFlag(kCpuHasMIPS_DSPR2) && (dst_width % 24 == 0) && | 329 if (TestCpuFlag(kCpuHasDSPR2) && (dst_width % 24 == 0) && |
330 IS_ALIGNED(src_ptr, 4) && IS_ALIGNED(src_stride, 4) && | 330 IS_ALIGNED(src_ptr, 4) && IS_ALIGNED(src_stride, 4) && |
331 IS_ALIGNED(dst_ptr, 4) && IS_ALIGNED(dst_stride, 4)) { | 331 IS_ALIGNED(dst_ptr, 4) && IS_ALIGNED(dst_stride, 4)) { |
332 if (!filtering) { | 332 if (!filtering) { |
333 ScaleRowDown34_0 = ScaleRowDown34_MIPS_DSPR2; | 333 ScaleRowDown34_0 = ScaleRowDown34_DSPR2; |
334 ScaleRowDown34_1 = ScaleRowDown34_MIPS_DSPR2; | 334 ScaleRowDown34_1 = ScaleRowDown34_DSPR2; |
335 } else { | 335 } else { |
336 ScaleRowDown34_0 = ScaleRowDown34_0_Box_MIPS_DSPR2; | 336 ScaleRowDown34_0 = ScaleRowDown34_0_Box_DSPR2; |
337 ScaleRowDown34_1 = ScaleRowDown34_1_Box_MIPS_DSPR2; | 337 ScaleRowDown34_1 = ScaleRowDown34_1_Box_DSPR2; |
338 } | 338 } |
339 } | 339 } |
340 #endif | 340 #endif |
341 | 341 |
342 for (y = 0; y < dst_height - 2; y += 3) { | 342 for (y = 0; y < dst_height - 2; y += 3) { |
343 ScaleRowDown34_0(src_ptr, filter_stride, dst_ptr, dst_width); | 343 ScaleRowDown34_0(src_ptr, filter_stride, dst_ptr, dst_width); |
344 src_ptr += src_stride; | 344 src_ptr += src_stride; |
345 dst_ptr += dst_stride; | 345 dst_ptr += dst_stride; |
346 ScaleRowDown34_1(src_ptr, filter_stride, dst_ptr, dst_width); | 346 ScaleRowDown34_1(src_ptr, filter_stride, dst_ptr, dst_width); |
347 src_ptr += src_stride; | 347 src_ptr += src_stride; |
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397 if (TestCpuFlag(kCpuHasSSSE3) && (dst_width % 24 == 0)) { | 397 if (TestCpuFlag(kCpuHasSSSE3) && (dst_width % 24 == 0)) { |
398 if (!filtering) { | 398 if (!filtering) { |
399 ScaleRowDown34_0 = ScaleRowDown34_16_SSSE3; | 399 ScaleRowDown34_0 = ScaleRowDown34_16_SSSE3; |
400 ScaleRowDown34_1 = ScaleRowDown34_16_SSSE3; | 400 ScaleRowDown34_1 = ScaleRowDown34_16_SSSE3; |
401 } else { | 401 } else { |
402 ScaleRowDown34_0 = ScaleRowDown34_0_Box_16_SSSE3; | 402 ScaleRowDown34_0 = ScaleRowDown34_0_Box_16_SSSE3; |
403 ScaleRowDown34_1 = ScaleRowDown34_1_Box_16_SSSE3; | 403 ScaleRowDown34_1 = ScaleRowDown34_1_Box_16_SSSE3; |
404 } | 404 } |
405 } | 405 } |
406 #endif | 406 #endif |
407 #if defined(HAS_SCALEROWDOWN34_16_MIPS_DSPR2) | 407 #if defined(HAS_SCALEROWDOWN34_16_DSPR2) |
408 if (TestCpuFlag(kCpuHasMIPS_DSPR2) && (dst_width % 24 == 0) && | 408 if (TestCpuFlag(kCpuHasDSPR2) && (dst_width % 24 == 0) && |
409 IS_ALIGNED(src_ptr, 4) && IS_ALIGNED(src_stride, 4) && | 409 IS_ALIGNED(src_ptr, 4) && IS_ALIGNED(src_stride, 4) && |
410 IS_ALIGNED(dst_ptr, 4) && IS_ALIGNED(dst_stride, 4)) { | 410 IS_ALIGNED(dst_ptr, 4) && IS_ALIGNED(dst_stride, 4)) { |
411 if (!filtering) { | 411 if (!filtering) { |
412 ScaleRowDown34_0 = ScaleRowDown34_16_MIPS_DSPR2; | 412 ScaleRowDown34_0 = ScaleRowDown34_16_DSPR2; |
413 ScaleRowDown34_1 = ScaleRowDown34_16_MIPS_DSPR2; | 413 ScaleRowDown34_1 = ScaleRowDown34_16_DSPR2; |
414 } else { | 414 } else { |
415 ScaleRowDown34_0 = ScaleRowDown34_0_Box_16_MIPS_DSPR2; | 415 ScaleRowDown34_0 = ScaleRowDown34_0_Box_16_DSPR2; |
416 ScaleRowDown34_1 = ScaleRowDown34_1_Box_16_MIPS_DSPR2; | 416 ScaleRowDown34_1 = ScaleRowDown34_1_Box_16_DSPR2; |
417 } | 417 } |
418 } | 418 } |
419 #endif | 419 #endif |
420 | 420 |
421 for (y = 0; y < dst_height - 2; y += 3) { | 421 for (y = 0; y < dst_height - 2; y += 3) { |
422 ScaleRowDown34_0(src_ptr, filter_stride, dst_ptr, dst_width); | 422 ScaleRowDown34_0(src_ptr, filter_stride, dst_ptr, dst_width); |
423 src_ptr += src_stride; | 423 src_ptr += src_stride; |
424 dst_ptr += dst_stride; | 424 dst_ptr += dst_stride; |
425 ScaleRowDown34_1(src_ptr, filter_stride, dst_ptr, dst_width); | 425 ScaleRowDown34_1(src_ptr, filter_stride, dst_ptr, dst_width); |
426 src_ptr += src_stride; | 426 src_ptr += src_stride; |
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510 if (dst_width % 12 == 0 && !filtering) { | 510 if (dst_width % 12 == 0 && !filtering) { |
511 ScaleRowDown38_3 = ScaleRowDown38_SSSE3; | 511 ScaleRowDown38_3 = ScaleRowDown38_SSSE3; |
512 ScaleRowDown38_2 = ScaleRowDown38_SSSE3; | 512 ScaleRowDown38_2 = ScaleRowDown38_SSSE3; |
513 } | 513 } |
514 if (dst_width % 6 == 0 && filtering) { | 514 if (dst_width % 6 == 0 && filtering) { |
515 ScaleRowDown38_3 = ScaleRowDown38_3_Box_SSSE3; | 515 ScaleRowDown38_3 = ScaleRowDown38_3_Box_SSSE3; |
516 ScaleRowDown38_2 = ScaleRowDown38_2_Box_SSSE3; | 516 ScaleRowDown38_2 = ScaleRowDown38_2_Box_SSSE3; |
517 } | 517 } |
518 } | 518 } |
519 #endif | 519 #endif |
520 #if defined(HAS_SCALEROWDOWN38_MIPS_DSPR2) | 520 #if defined(HAS_SCALEROWDOWN38_DSPR2) |
521 if (TestCpuFlag(kCpuHasMIPS_DSPR2) && (dst_width % 12 == 0) && | 521 if (TestCpuFlag(kCpuHasDSPR2) && (dst_width % 12 == 0) && |
522 IS_ALIGNED(src_ptr, 4) && IS_ALIGNED(src_stride, 4) && | 522 IS_ALIGNED(src_ptr, 4) && IS_ALIGNED(src_stride, 4) && |
523 IS_ALIGNED(dst_ptr, 4) && IS_ALIGNED(dst_stride, 4)) { | 523 IS_ALIGNED(dst_ptr, 4) && IS_ALIGNED(dst_stride, 4)) { |
524 if (!filtering) { | 524 if (!filtering) { |
525 ScaleRowDown38_3 = ScaleRowDown38_MIPS_DSPR2; | 525 ScaleRowDown38_3 = ScaleRowDown38_DSPR2; |
526 ScaleRowDown38_2 = ScaleRowDown38_MIPS_DSPR2; | 526 ScaleRowDown38_2 = ScaleRowDown38_DSPR2; |
527 } else { | 527 } else { |
528 ScaleRowDown38_3 = ScaleRowDown38_3_Box_MIPS_DSPR2; | 528 ScaleRowDown38_3 = ScaleRowDown38_3_Box_DSPR2; |
529 ScaleRowDown38_2 = ScaleRowDown38_2_Box_MIPS_DSPR2; | 529 ScaleRowDown38_2 = ScaleRowDown38_2_Box_DSPR2; |
530 } | 530 } |
531 } | 531 } |
532 #endif | 532 #endif |
533 | 533 |
534 for (y = 0; y < dst_height - 2; y += 3) { | 534 for (y = 0; y < dst_height - 2; y += 3) { |
535 ScaleRowDown38_3(src_ptr, filter_stride, dst_ptr, dst_width); | 535 ScaleRowDown38_3(src_ptr, filter_stride, dst_ptr, dst_width); |
536 src_ptr += src_stride * 3; | 536 src_ptr += src_stride * 3; |
537 dst_ptr += dst_stride; | 537 dst_ptr += dst_stride; |
538 ScaleRowDown38_3(src_ptr, filter_stride, dst_ptr, dst_width); | 538 ScaleRowDown38_3(src_ptr, filter_stride, dst_ptr, dst_width); |
539 src_ptr += src_stride * 3; | 539 src_ptr += src_stride * 3; |
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588 if (TestCpuFlag(kCpuHasSSSE3) && (dst_width % 24 == 0)) { | 588 if (TestCpuFlag(kCpuHasSSSE3) && (dst_width % 24 == 0)) { |
589 if (!filtering) { | 589 if (!filtering) { |
590 ScaleRowDown38_3 = ScaleRowDown38_16_SSSE3; | 590 ScaleRowDown38_3 = ScaleRowDown38_16_SSSE3; |
591 ScaleRowDown38_2 = ScaleRowDown38_16_SSSE3; | 591 ScaleRowDown38_2 = ScaleRowDown38_16_SSSE3; |
592 } else { | 592 } else { |
593 ScaleRowDown38_3 = ScaleRowDown38_3_Box_16_SSSE3; | 593 ScaleRowDown38_3 = ScaleRowDown38_3_Box_16_SSSE3; |
594 ScaleRowDown38_2 = ScaleRowDown38_2_Box_16_SSSE3; | 594 ScaleRowDown38_2 = ScaleRowDown38_2_Box_16_SSSE3; |
595 } | 595 } |
596 } | 596 } |
597 #endif | 597 #endif |
598 #if defined(HAS_SCALEROWDOWN38_16_MIPS_DSPR2) | 598 #if defined(HAS_SCALEROWDOWN38_16_DSPR2) |
599 if (TestCpuFlag(kCpuHasMIPS_DSPR2) && (dst_width % 12 == 0) && | 599 if (TestCpuFlag(kCpuHasDSPR2) && (dst_width % 12 == 0) && |
600 IS_ALIGNED(src_ptr, 4) && IS_ALIGNED(src_stride, 4) && | 600 IS_ALIGNED(src_ptr, 4) && IS_ALIGNED(src_stride, 4) && |
601 IS_ALIGNED(dst_ptr, 4) && IS_ALIGNED(dst_stride, 4)) { | 601 IS_ALIGNED(dst_ptr, 4) && IS_ALIGNED(dst_stride, 4)) { |
602 if (!filtering) { | 602 if (!filtering) { |
603 ScaleRowDown38_3 = ScaleRowDown38_16_MIPS_DSPR2; | 603 ScaleRowDown38_3 = ScaleRowDown38_16_DSPR2; |
604 ScaleRowDown38_2 = ScaleRowDown38_16_MIPS_DSPR2; | 604 ScaleRowDown38_2 = ScaleRowDown38_16_DSPR2; |
605 } else { | 605 } else { |
606 ScaleRowDown38_3 = ScaleRowDown38_3_Box_16_MIPS_DSPR2; | 606 ScaleRowDown38_3 = ScaleRowDown38_3_Box_16_DSPR2; |
607 ScaleRowDown38_2 = ScaleRowDown38_2_Box_16_MIPS_DSPR2; | 607 ScaleRowDown38_2 = ScaleRowDown38_2_Box_16_DSPR2; |
608 } | 608 } |
609 } | 609 } |
610 #endif | 610 #endif |
611 | 611 |
612 for (y = 0; y < dst_height - 2; y += 3) { | 612 for (y = 0; y < dst_height - 2; y += 3) { |
613 ScaleRowDown38_3(src_ptr, filter_stride, dst_ptr, dst_width); | 613 ScaleRowDown38_3(src_ptr, filter_stride, dst_ptr, dst_width); |
614 src_ptr += src_stride * 3; | 614 src_ptr += src_stride * 3; |
615 dst_ptr += dst_stride; | 615 dst_ptr += dst_stride; |
616 ScaleRowDown38_3(src_ptr, filter_stride, dst_ptr, dst_width); | 616 ScaleRowDown38_3(src_ptr, filter_stride, dst_ptr, dst_width); |
617 src_ptr += src_stride * 3; | 617 src_ptr += src_stride * 3; |
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891 } | 891 } |
892 #endif | 892 #endif |
893 #if defined(HAS_INTERPOLATEROW_NEON) | 893 #if defined(HAS_INTERPOLATEROW_NEON) |
894 if (TestCpuFlag(kCpuHasNEON)) { | 894 if (TestCpuFlag(kCpuHasNEON)) { |
895 InterpolateRow = InterpolateRow_Any_NEON; | 895 InterpolateRow = InterpolateRow_Any_NEON; |
896 if (IS_ALIGNED(src_width, 16)) { | 896 if (IS_ALIGNED(src_width, 16)) { |
897 InterpolateRow = InterpolateRow_NEON; | 897 InterpolateRow = InterpolateRow_NEON; |
898 } | 898 } |
899 } | 899 } |
900 #endif | 900 #endif |
901 #if defined(HAS_INTERPOLATEROW_MIPS_DSPR2) | 901 #if defined(HAS_INTERPOLATEROW_DSPR2) |
902 if (TestCpuFlag(kCpuHasMIPS_DSPR2)) { | 902 if (TestCpuFlag(kCpuHasDSPR2)) { |
903 InterpolateRow = InterpolateRow_Any_MIPS_DSPR2; | 903 InterpolateRow = InterpolateRow_Any_DSPR2; |
904 if (IS_ALIGNED(src_width, 4)) { | 904 if (IS_ALIGNED(src_width, 4)) { |
905 InterpolateRow = InterpolateRow_MIPS_DSPR2; | 905 InterpolateRow = InterpolateRow_DSPR2; |
906 } | 906 } |
907 } | 907 } |
908 #endif | 908 #endif |
909 | 909 |
910 | 910 |
911 #if defined(HAS_SCALEFILTERCOLS_SSSE3) | 911 #if defined(HAS_SCALEFILTERCOLS_SSSE3) |
912 if (TestCpuFlag(kCpuHasSSSE3) && src_width < 32768) { | 912 if (TestCpuFlag(kCpuHasSSSE3) && src_width < 32768) { |
913 ScaleFilterCols = ScaleFilterCols_SSSE3; | 913 ScaleFilterCols = ScaleFilterCols_SSSE3; |
914 } | 914 } |
915 #endif | 915 #endif |
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995 } | 995 } |
996 #endif | 996 #endif |
997 #if defined(HAS_INTERPOLATEROW_16_NEON) | 997 #if defined(HAS_INTERPOLATEROW_16_NEON) |
998 if (TestCpuFlag(kCpuHasNEON)) { | 998 if (TestCpuFlag(kCpuHasNEON)) { |
999 InterpolateRow = InterpolateRow_Any_16_NEON; | 999 InterpolateRow = InterpolateRow_Any_16_NEON; |
1000 if (IS_ALIGNED(src_width, 16)) { | 1000 if (IS_ALIGNED(src_width, 16)) { |
1001 InterpolateRow = InterpolateRow_16_NEON; | 1001 InterpolateRow = InterpolateRow_16_NEON; |
1002 } | 1002 } |
1003 } | 1003 } |
1004 #endif | 1004 #endif |
1005 #if defined(HAS_INTERPOLATEROW_16_MIPS_DSPR2) | 1005 #if defined(HAS_INTERPOLATEROW_16_DSPR2) |
1006 if (TestCpuFlag(kCpuHasMIPS_DSPR2)) { | 1006 if (TestCpuFlag(kCpuHasDSPR2)) { |
1007 InterpolateRow = InterpolateRow_Any_16_MIPS_DSPR2; | 1007 InterpolateRow = InterpolateRow_Any_16_DSPR2; |
1008 if (IS_ALIGNED(src_width, 4)) { | 1008 if (IS_ALIGNED(src_width, 4)) { |
1009 InterpolateRow = InterpolateRow_16_MIPS_DSPR2; | 1009 InterpolateRow = InterpolateRow_16_DSPR2; |
1010 } | 1010 } |
1011 } | 1011 } |
1012 #endif | 1012 #endif |
1013 | 1013 |
1014 | 1014 |
1015 #if defined(HAS_SCALEFILTERCOLS_16_SSSE3) | 1015 #if defined(HAS_SCALEFILTERCOLS_16_SSSE3) |
1016 if (TestCpuFlag(kCpuHasSSSE3) && src_width < 32768) { | 1016 if (TestCpuFlag(kCpuHasSSSE3) && src_width < 32768) { |
1017 ScaleFilterCols = ScaleFilterCols_16_SSSE3; | 1017 ScaleFilterCols = ScaleFilterCols_16_SSSE3; |
1018 } | 1018 } |
1019 #endif | 1019 #endif |
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1080 } | 1080 } |
1081 #endif | 1081 #endif |
1082 #if defined(HAS_INTERPOLATEROW_NEON) | 1082 #if defined(HAS_INTERPOLATEROW_NEON) |
1083 if (TestCpuFlag(kCpuHasNEON)) { | 1083 if (TestCpuFlag(kCpuHasNEON)) { |
1084 InterpolateRow = InterpolateRow_Any_NEON; | 1084 InterpolateRow = InterpolateRow_Any_NEON; |
1085 if (IS_ALIGNED(dst_width, 16)) { | 1085 if (IS_ALIGNED(dst_width, 16)) { |
1086 InterpolateRow = InterpolateRow_NEON; | 1086 InterpolateRow = InterpolateRow_NEON; |
1087 } | 1087 } |
1088 } | 1088 } |
1089 #endif | 1089 #endif |
1090 #if defined(HAS_INTERPOLATEROW_MIPS_DSPR2) | 1090 #if defined(HAS_INTERPOLATEROW_DSPR2) |
1091 if (TestCpuFlag(kCpuHasMIPS_DSPR2)) { | 1091 if (TestCpuFlag(kCpuHasDSPR2)) { |
1092 InterpolateRow = InterpolateRow_Any_MIPS_DSPR2; | 1092 InterpolateRow = InterpolateRow_Any_DSPR2; |
1093 if (IS_ALIGNED(dst_width, 4)) { | 1093 if (IS_ALIGNED(dst_width, 4)) { |
1094 InterpolateRow = InterpolateRow_MIPS_DSPR2; | 1094 InterpolateRow = InterpolateRow_DSPR2; |
1095 } | 1095 } |
1096 } | 1096 } |
1097 #endif | 1097 #endif |
1098 | 1098 |
1099 if (filtering && src_width >= 32768) { | 1099 if (filtering && src_width >= 32768) { |
1100 ScaleFilterCols = ScaleFilterCols64_C; | 1100 ScaleFilterCols = ScaleFilterCols64_C; |
1101 } | 1101 } |
1102 #if defined(HAS_SCALEFILTERCOLS_SSSE3) | 1102 #if defined(HAS_SCALEFILTERCOLS_SSSE3) |
1103 if (filtering && TestCpuFlag(kCpuHasSSSE3) && src_width < 32768) { | 1103 if (filtering && TestCpuFlag(kCpuHasSSSE3) && src_width < 32768) { |
1104 ScaleFilterCols = ScaleFilterCols_SSSE3; | 1104 ScaleFilterCols = ScaleFilterCols_SSSE3; |
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1219 } | 1219 } |
1220 #endif | 1220 #endif |
1221 #if defined(HAS_INTERPOLATEROW_16_NEON) | 1221 #if defined(HAS_INTERPOLATEROW_16_NEON) |
1222 if (TestCpuFlag(kCpuHasNEON)) { | 1222 if (TestCpuFlag(kCpuHasNEON)) { |
1223 InterpolateRow = InterpolateRow_Any_16_NEON; | 1223 InterpolateRow = InterpolateRow_Any_16_NEON; |
1224 if (IS_ALIGNED(dst_width, 16)) { | 1224 if (IS_ALIGNED(dst_width, 16)) { |
1225 InterpolateRow = InterpolateRow_16_NEON; | 1225 InterpolateRow = InterpolateRow_16_NEON; |
1226 } | 1226 } |
1227 } | 1227 } |
1228 #endif | 1228 #endif |
1229 #if defined(HAS_INTERPOLATEROW_16_MIPS_DSPR2) | 1229 #if defined(HAS_INTERPOLATEROW_16_DSPR2) |
1230 if (TestCpuFlag(kCpuHasMIPS_DSPR2)) { | 1230 if (TestCpuFlag(kCpuHasDSPR2)) { |
1231 InterpolateRow = InterpolateRow_Any_16_MIPS_DSPR2; | 1231 InterpolateRow = InterpolateRow_Any_16_DSPR2; |
1232 if (IS_ALIGNED(dst_width, 4)) { | 1232 if (IS_ALIGNED(dst_width, 4)) { |
1233 InterpolateRow = InterpolateRow_16_MIPS_DSPR2; | 1233 InterpolateRow = InterpolateRow_16_DSPR2; |
1234 } | 1234 } |
1235 } | 1235 } |
1236 #endif | 1236 #endif |
1237 | 1237 |
1238 if (filtering && src_width >= 32768) { | 1238 if (filtering && src_width >= 32768) { |
1239 ScaleFilterCols = ScaleFilterCols64_16_C; | 1239 ScaleFilterCols = ScaleFilterCols64_16_C; |
1240 } | 1240 } |
1241 #if defined(HAS_SCALEFILTERCOLS_16_SSSE3) | 1241 #if defined(HAS_SCALEFILTERCOLS_16_SSSE3) |
1242 if (filtering && TestCpuFlag(kCpuHasSSSE3) && src_width < 32768) { | 1242 if (filtering && TestCpuFlag(kCpuHasSSSE3) && src_width < 32768) { |
1243 ScaleFilterCols = ScaleFilterCols_16_SSSE3; | 1243 ScaleFilterCols = ScaleFilterCols_16_SSSE3; |
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1663 dst_u, dst_halfwidth, | 1663 dst_u, dst_halfwidth, |
1664 dst_v, dst_halfwidth, | 1664 dst_v, dst_halfwidth, |
1665 dst_width, aheight, | 1665 dst_width, aheight, |
1666 interpolate ? kFilterBox : kFilterNone); | 1666 interpolate ? kFilterBox : kFilterNone); |
1667 } | 1667 } |
1668 | 1668 |
1669 #ifdef __cplusplus | 1669 #ifdef __cplusplus |
1670 } // extern "C" | 1670 } // extern "C" |
1671 } // namespace libyuv | 1671 } // namespace libyuv |
1672 #endif | 1672 #endif |
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