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Side by Side Diff: src/IceTargetLoweringX86BaseImpl.h

Issue 1677593003: Subzero: Improve an error message. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 4 years, 10 months ago
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1 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==// 1 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 /// 9 ///
10 /// \file 10 /// \file
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877 Ostream &Str = Ctx->getStrEmit(); 877 Ostream &Str = Ctx->getStrEmit();
878 if (Var->hasReg()) { 878 if (Var->hasReg()) {
879 const bool Is64BitSandboxing = Traits::Is64Bit && NeedSandboxing; 879 const bool Is64BitSandboxing = Traits::Is64Bit && NeedSandboxing;
880 const Type VarType = (Var->isRematerializable() && Is64BitSandboxing) 880 const Type VarType = (Var->isRematerializable() && Is64BitSandboxing)
881 ? IceType_i64 881 ? IceType_i64
882 : Var->getType(); 882 : Var->getType();
883 Str << "%" << getRegName(Var->getRegNum(), VarType); 883 Str << "%" << getRegName(Var->getRegNum(), VarType);
884 return; 884 return;
885 } 885 }
886 if (Var->mustHaveReg()) { 886 if (Var->mustHaveReg()) {
887 llvm::report_fatal_error( 887 llvm::report_fatal_error("Infinite-weight Variable (" + Var->getName(Func) +
888 "Infinite-weight Variable has no register assigned"); 888 ") has no register assigned - function " +
889 Func->getFunctionName());
889 } 890 }
890 const int32_t Offset = Var->getStackOffset(); 891 const int32_t Offset = Var->getStackOffset();
891 int32_t BaseRegNum = Var->getBaseRegNum(); 892 int32_t BaseRegNum = Var->getBaseRegNum();
892 if (BaseRegNum == Variable::NoRegister) 893 if (BaseRegNum == Variable::NoRegister)
893 BaseRegNum = getFrameOrStackReg(); 894 BaseRegNum = getFrameOrStackReg();
894 // Print in the form "Offset(%reg)", taking care that: 895 // Print in the form "Offset(%reg)", taking care that:
895 // - Offset is never printed when it is 0 896 // - Offset is never printed when it is 0
896 897
897 const bool DecorateAsm = Func->getContext()->getFlags().getDecorateAsm(); 898 const bool DecorateAsm = Func->getContext()->getFlags().getDecorateAsm();
898 // Only print Offset when it is nonzero, regardless of DecorateAsm. 899 // Only print Offset when it is nonzero, regardless of DecorateAsm.
899 if (Offset) { 900 if (Offset) {
900 if (DecorateAsm) { 901 if (DecorateAsm) {
901 Str << Var->getSymbolicStackOffset(Func); 902 Str << Var->getSymbolicStackOffset(Func);
902 } else { 903 } else {
903 Str << Offset; 904 Str << Offset;
904 } 905 }
905 } 906 }
906 const Type FrameSPTy = Traits::WordType; 907 const Type FrameSPTy = Traits::WordType;
907 Str << "(%" << getRegName(BaseRegNum, FrameSPTy) << ")"; 908 Str << "(%" << getRegName(BaseRegNum, FrameSPTy) << ")";
908 } 909 }
909 910
910 template <typename TraitsType> 911 template <typename TraitsType>
911 typename TargetX86Base<TraitsType>::X86Address 912 typename TargetX86Base<TraitsType>::X86Address
912 TargetX86Base<TraitsType>::stackVarToAsmOperand(const Variable *Var) const { 913 TargetX86Base<TraitsType>::stackVarToAsmOperand(const Variable *Var) const {
913 if (Var->hasReg()) 914 if (Var->hasReg())
914 llvm::report_fatal_error("Stack Variable has a register assigned"); 915 llvm::report_fatal_error("Stack Variable has a register assigned");
915 if (Var->mustHaveReg()) { 916 if (Var->mustHaveReg()) {
916 llvm::report_fatal_error( 917 llvm::report_fatal_error("Infinite-weight Variable (" + Var->getName(Func) +
917 "Infinite-weight Variable has no register assigned"); 918 ") has no register assigned - function " +
919 Func->getFunctionName());
918 } 920 }
919 int32_t Offset = Var->getStackOffset(); 921 int32_t Offset = Var->getStackOffset();
920 int32_t BaseRegNum = Var->getBaseRegNum(); 922 int32_t BaseRegNum = Var->getBaseRegNum();
921 if (Var->getBaseRegNum() == Variable::NoRegister) 923 if (Var->getBaseRegNum() == Variable::NoRegister)
922 BaseRegNum = getFrameOrStackReg(); 924 BaseRegNum = getFrameOrStackReg();
923 return X86Address(Traits::getEncodedGPR(BaseRegNum), Offset, 925 return X86Address(Traits::getEncodedGPR(BaseRegNum), Offset,
924 AssemblerFixup::NoFixup); 926 AssemblerFixup::NoFixup);
925 } 927 }
926 928
927 template <typename TraitsType> 929 template <typename TraitsType>
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7455 emitGlobal(*Var, SectionSuffix); 7457 emitGlobal(*Var, SectionSuffix);
7456 } 7458 }
7457 } 7459 }
7458 } break; 7460 } break;
7459 } 7461 }
7460 } 7462 }
7461 } // end of namespace X86NAMESPACE 7463 } // end of namespace X86NAMESPACE
7462 } // end of namespace Ice 7464 } // end of namespace Ice
7463 7465
7464 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H 7466 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H
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