| Index: src/IceInstARM32.cpp
|
| diff --git a/src/IceInstARM32.cpp b/src/IceInstARM32.cpp
|
| index 6b9c5a0ab545e4fb4f66b07bfa0f88bac954a908..e6b0f5f0d52af401abdbc6787810183d3b304185 100644
|
| --- a/src/IceInstARM32.cpp
|
| +++ b/src/IceInstARM32.cpp
|
| @@ -888,13 +888,13 @@ void InstARM32RegisterStackOp::emitSRegsAsText(const Cfg *Func,
|
| Ostream &Str = Func->getContext()->getStrEmit();
|
| Str << "\t" << getSRegOpcode() << "\t{";
|
| bool IsFirst = true;
|
| - int32_t Base = BaseReg->getRegNum();
|
| + RegNumT Base = BaseReg->getRegNum();
|
| for (SizeT i = 0; i < RegCount; ++i) {
|
| if (IsFirst)
|
| IsFirst = false;
|
| else
|
| Str << ", ";
|
| - Str << RegARM32::getRegName(Base + i);
|
| + Str << RegARM32::getRegName(RegNumT::fixme(Base + i));
|
| }
|
| Str << "}";
|
| }
|
| @@ -905,7 +905,7 @@ bool isAssignedConsecutiveRegisters(const Variable *Before,
|
| const Variable *After) {
|
| assert(Before->hasReg());
|
| assert(After->hasReg());
|
| - return Before->getRegNum() + 1 == After->getRegNum();
|
| + return RegNumT::fixme(Before->getRegNum() + 1) == After->getRegNum();
|
| }
|
|
|
| } // end of anonymous namespace
|
| @@ -924,7 +924,7 @@ void InstARM32RegisterStackOp::emitUsingForm(const Cfg *Func,
|
| for (SizeT i = 0; i < NumRegs; ++i) {
|
| const Variable *Var = getStackReg(i);
|
| assert(Var->hasReg() && "stack op only applies to registers");
|
| - int32_t Reg = RegARM32::getEncodedGPR(Var->getRegNum());
|
| + RegARM32::GPRRegister Reg = RegARM32::getEncodedGPR(Var->getRegNum());
|
| LastDest = Var;
|
| GPRegisters |= (1 << Reg);
|
| ++IntegerCount;
|
|
|