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Unified Diff: src/IceRegAlloc.cpp

Issue 1676123002: Subzero: Use a proper RegNumT type instead of int32_t/SizeT. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Revert some method name changes Created 4 years, 10 months ago
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« src/IceOperand.h ('K') | « src/IceRegAlloc.h ('k') | src/IceRegistersARM32.h » ('j') | src/IceTargetLoweringX8664Traits.h » ('J')
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Index: src/IceRegAlloc.cpp
diff --git a/src/IceRegAlloc.cpp b/src/IceRegAlloc.cpp
index ced9af5474d8f193078018285ef278f76d630089..16e7dd92a7802fd1ca201d70d4d156a6372f9cb2 100644
--- a/src/IceRegAlloc.cpp
+++ b/src/IceRegAlloc.cpp
@@ -70,7 +70,8 @@ void dumpLiveRange(const Variable *Var, const Cfg *Func) {
return;
Ostream &Str = Func->getContext()->getStrDump();
char buf[30];
- snprintf(buf, llvm::array_lengthof(buf), "%2d", Var->getRegNumTmp());
+ snprintf(buf, llvm::array_lengthof(buf), "%2u",
+ unsigned(Var->getRegNumTmp()));
Str << "R=" << buf << " V=";
Var->dump(Func);
Str << " Range=" << Var->getLiveRange();
@@ -79,9 +80,9 @@ void dumpLiveRange(const Variable *Var, const Cfg *Func) {
int32_t findMinWeightIndex(
const llvm::SmallBitVector &RegMask,
const llvm::SmallVector<RegWeight, LinearScan::REGS_SIZE> &Weights) {
- int32_t MinWeightIndex = RegMask.find_first();
+ int MinWeightIndex = RegMask.find_first();
assert(MinWeightIndex >= 0);
- for (int32_t i = RegMask.find_next(MinWeightIndex); i != -1;
+ for (int i = RegMask.find_next(MinWeightIndex); i != -1;
i = RegMask.find_next(i)) {
if (Weights[i] < Weights[MinWeightIndex])
MinWeightIndex = i;
@@ -332,7 +333,7 @@ void LinearScan::init(RegAllocKind Kind) {
SizeT NumRegs = Target->getNumRegisters();
RegAliases.resize(NumRegs);
for (SizeT Reg = 0; Reg < NumRegs; ++Reg) {
- RegAliases[Reg] = &Target->getAliasesForRegister(Reg);
+ RegAliases[Reg] = &Target->getAliasesForRegister(RegNumT::fromInt(Reg));
}
switch (Kind) {
@@ -414,8 +415,7 @@ void LinearScan::addSpillFill(IterationState &Iter) {
if (!Var->hasRegTmp())
continue;
const llvm::SmallBitVector &Aliases = *RegAliases[Var->getRegNumTmp()];
- for (int32_t RegAlias = Aliases.find_first(); RegAlias >= 0;
- RegAlias = Aliases.find_next(RegAlias)) {
+ for (RegNumT RegAlias : RegNumBitVector(Aliases)) {
Iter.RegMask[RegAlias] = false;
}
}
@@ -425,8 +425,7 @@ void LinearScan::addSpillFill(IterationState &Iter) {
assert(FillPoint != Insts.end());
++FillPoint;
// TODO(stichnot): Randomize instead of find_first().
John 2016/02/10 16:01:51 update the comment.
Jim Stichnoth 2016/02/10 17:47:20 Done.
- int32_t RegNum = Iter.RegMask.find_first();
- assert(RegNum != -1);
+ RegNumT RegNum = *RegNumBitVector(Iter.RegMask).begin();
Iter.Cur->setRegNumTmp(RegNum);
Variable *Preg = Target->getPhysicalRegister(RegNum, Iter.Cur->getType());
// TODO(stichnot): Add SpillLoc to VariablesMetadata tracking so that SpillLoc
@@ -461,8 +460,7 @@ void LinearScan::handleActiveRangeExpiredOrInactive(const Variable *Cur) {
// Decrement Item from RegUses[].
assert(Item->hasRegTmp());
const llvm::SmallBitVector &Aliases = *RegAliases[Item->getRegNumTmp()];
- for (int32_t RegAlias = Aliases.find_first(); RegAlias >= 0;
- RegAlias = Aliases.find_next(RegAlias)) {
+ for (RegNumT RegAlias : RegNumBitVector(Aliases)) {
--RegUses[RegAlias];
assert(RegUses[RegAlias] >= 0);
}
@@ -486,8 +484,7 @@ void LinearScan::handleInactiveRangeExpiredOrReactivated(const Variable *Cur) {
// Increment Item in RegUses[].
assert(Item->hasRegTmp());
const llvm::SmallBitVector &Aliases = *RegAliases[Item->getRegNumTmp()];
- for (int32_t RegAlias = Aliases.find_first(); RegAlias >= 0;
- RegAlias = Aliases.find_next(RegAlias)) {
+ for (RegNumT RegAlias : RegNumBitVector(Aliases)) {
assert(RegUses[RegAlias] >= 0);
++RegUses[RegAlias];
}
@@ -506,7 +503,7 @@ void LinearScan::handleInactiveRangeExpiredOrReactivated(const Variable *Cur) {
// not appear within the current Variable's live range.
void LinearScan::findRegisterPreference(IterationState &Iter) {
Iter.Prefer = nullptr;
- Iter.PreferReg = Variable::NoRegister;
+ Iter.PreferReg = RegNumT::NoRegister;
Iter.AllowOverlap = false;
if (!FindPreference)
@@ -529,7 +526,7 @@ void LinearScan::findRegisterPreference(IterationState &Iter) {
// That register must be one in the RegMask set, e.g. don't try to prefer
// the stack pointer as a result of the stacksave intrinsic.
const llvm::SmallBitVector &Aliases = *RegAliases[SrcVar->getRegNumTmp()];
- const int32_t SrcReg = (Iter.RegMask & Aliases).find_first();
+ const int SrcReg = (Iter.RegMask & Aliases).find_first();
if (SrcReg == -1)
continue;
@@ -540,7 +537,7 @@ void LinearScan::findRegisterPreference(IterationState &Iter) {
}
if (Iter.AllowOverlap || Iter.Free[SrcReg]) {
Iter.Prefer = SrcVar;
- Iter.PreferReg = SrcReg;
+ Iter.PreferReg = RegNumT::fromInt(SrcReg);
// Stop looking for a preference after the first valid preference is
// found. One might think that we should look at all instruction
// variables to find the best <Prefer,AllowOverlap> combination, but note
@@ -566,10 +563,8 @@ void LinearScan::filterFreeWithInactiveRanges(IterationState &Iter) {
if (!Item->rangeOverlaps(Iter.Cur))
continue;
const llvm::SmallBitVector &Aliases = *RegAliases[Item->getRegNumTmp()];
- // TODO(stichnot): Do this with bitvector ops, not a loop, for efficiency.
- for (int32_t RegAlias = Aliases.find_first(); RegAlias >= 0;
- RegAlias = Aliases.find_next(RegAlias)) {
- // Don't assert(Iter.Free[RegNum]) because in theory (though probably
+ for (RegNumT RegAlias : RegNumBitVector(Aliases)) {
+ // Don't assert(Iter.Free[RegAlias]) because in theory (though probably
// never in practice) there could be two inactive variables that were
// marked with AllowOverlap.
Iter.Free[RegAlias] = false;
@@ -601,8 +596,7 @@ void LinearScan::filterFreeWithPrecoloredRanges(IterationState &Iter) {
continue;
const llvm::SmallBitVector &Aliases =
*RegAliases[Item->getRegNum()]; // Note: not getRegNumTmp()
- for (int32_t RegAlias = Aliases.find_first(); RegAlias >= 0;
- RegAlias = Aliases.find_next(RegAlias)) {
+ for (RegNumT RegAlias : RegNumBitVector(Aliases)) {
Iter.Weights[RegAlias].setWeight(RegWeight::Inf);
Iter.Free[RegAlias] = false;
Iter.FreeUnfiltered[RegAlias] = false;
@@ -618,14 +612,13 @@ void LinearScan::filterFreeWithPrecoloredRanges(IterationState &Iter) {
}
void LinearScan::allocatePrecoloredRegister(Variable *Cur) {
- int32_t RegNum = Cur->getRegNum();
+ auto RegNum = Cur->getRegNum();
// RegNumTmp should have already been set above.
assert(Cur->getRegNumTmp() == RegNum);
dumpLiveRangeTrace("Precoloring ", Cur);
Active.push_back(Cur);
const llvm::SmallBitVector &Aliases = *RegAliases[RegNum];
- for (int32_t RegAlias = Aliases.find_first(); RegAlias >= 0;
- RegAlias = Aliases.find_next(RegAlias)) {
+ for (RegNumT RegAlias : RegNumBitVector(Aliases)) {
John 2016/02/10 16:01:51 just curious why this is not auto, but everywhere
Jim Stichnoth 2016/02/10 17:47:20 I prefer being more explicit with range-based for
assert(RegUses[RegAlias] >= 0);
++RegUses[RegAlias];
}
@@ -638,8 +631,7 @@ void LinearScan::allocatePreferredRegister(IterationState &Iter) {
Iter.Cur->setRegNumTmp(Iter.PreferReg);
dumpLiveRangeTrace("Preferring ", Iter.Cur);
const llvm::SmallBitVector &Aliases = *RegAliases[Iter.PreferReg];
- for (int32_t RegAlias = Aliases.find_first(); RegAlias >= 0;
- RegAlias = Aliases.find_next(RegAlias)) {
+ for (RegNumT RegAlias : RegNumBitVector(Aliases)) {
assert(RegUses[RegAlias] >= 0);
++RegUses[RegAlias];
}
@@ -647,16 +639,15 @@ void LinearScan::allocatePreferredRegister(IterationState &Iter) {
}
void LinearScan::allocateFreeRegister(IterationState &Iter, bool Filtered) {
- const int32_t RegNum =
- Filtered ? Iter.Free.find_first() : Iter.FreeUnfiltered.find_first();
+ const RegNumT RegNum =
+ *RegNumBitVector(Filtered ? Iter.Free : Iter.FreeUnfiltered).begin();
Iter.Cur->setRegNumTmp(RegNum);
if (Filtered)
dumpLiveRangeTrace("Allocating ", Iter.Cur);
else
dumpLiveRangeTrace("Allocating X ", Iter.Cur);
const llvm::SmallBitVector &Aliases = *RegAliases[RegNum];
- for (int32_t RegAlias = Aliases.find_first(); RegAlias >= 0;
- RegAlias = Aliases.find_next(RegAlias)) {
+ for (RegNumT RegAlias : RegNumBitVector(Aliases)) {
assert(RegUses[RegAlias] >= 0);
++RegUses[RegAlias];
}
@@ -673,8 +664,7 @@ void LinearScan::handleNoFreeRegisters(IterationState &Iter) {
// should we decide to pick any of them, then we would incur that many
// memory accesses.
RegWeight W = Item->getWeight(Func);
- for (int32_t RegAlias = Aliases.find_first(); RegAlias >= 0;
- RegAlias = Aliases.find_next(RegAlias)) {
+ for (RegNumT RegAlias : RegNumBitVector(Aliases)) {
Iter.Weights[RegAlias].addWeight(W);
}
}
@@ -685,8 +675,7 @@ void LinearScan::handleNoFreeRegisters(IterationState &Iter) {
assert(Item->hasRegTmp());
const llvm::SmallBitVector &Aliases = *RegAliases[Item->getRegNumTmp()];
RegWeight W = Item->getWeight(Func);
- for (int32_t RegAlias = Aliases.find_first(); RegAlias >= 0;
- RegAlias = Aliases.find_next(RegAlias)) {
+ for (RegNumT RegAlias : RegNumBitVector(Aliases)) {
Iter.Weights[RegAlias].addWeight(W);
}
}
@@ -742,16 +731,15 @@ void LinearScan::handleNoFreeRegisters(IterationState &Iter) {
for (SizeT I = Active.size(); I > 0; --I) {
const SizeT Index = I - 1;
Variable *Item = Active[Index];
- int32_t RegNum = Item->getRegNumTmp();
+ auto RegNum = Item->getRegNumTmp();
if (Aliases[RegNum]) {
dumpLiveRangeTrace("Evicting A ", Item);
const llvm::SmallBitVector &Aliases = *RegAliases[RegNum];
- for (int32_t RegAlias = Aliases.find_first(); RegAlias >= 0;
- RegAlias = Aliases.find_next(RegAlias)) {
+ for (RegNumT RegAlias : RegNumBitVector(Aliases)) {
--RegUses[RegAlias];
assert(RegUses[RegAlias] >= 0);
}
- Item->setRegNumTmp(Variable::NoRegister);
+ Item->setRegNumTmp(RegNumT::NoRegister);
moveItem(Active, Index, Handled);
Evicted.push_back(Item);
}
@@ -769,15 +757,14 @@ void LinearScan::handleNoFreeRegisters(IterationState &Iter) {
// instructions.
if (Aliases[Item->getRegNumTmp()] && Item->rangeOverlaps(Iter.Cur)) {
dumpLiveRangeTrace("Evicting I ", Item);
- Item->setRegNumTmp(Variable::NoRegister);
+ Item->setRegNumTmp(RegNumT::NoRegister);
moveItem(Inactive, Index, Handled);
Evicted.push_back(Item);
}
}
// Assign the register to Cur.
- Iter.Cur->setRegNumTmp(MinWeightIndex);
- for (int32_t RegAlias = Aliases.find_first(); RegAlias >= 0;
- RegAlias = Aliases.find_next(RegAlias)) {
+ Iter.Cur->setRegNumTmp(RegNumT::fromInt(MinWeightIndex));
+ for (RegNumT RegAlias : RegNumBitVector(Aliases)) {
assert(RegUses[RegAlias] >= 0);
++RegUses[RegAlias];
}
@@ -789,7 +776,7 @@ void LinearScan::assignFinalRegisters(
const llvm::SmallBitVector &RegMaskFull,
const llvm::SmallBitVector &PreDefinedRegisters, bool Randomized) {
const size_t NumRegisters = RegMaskFull.size();
- llvm::SmallVector<int32_t, REGS_SIZE> Permutation(NumRegisters);
+ llvm::SmallVector<RegNumT, REGS_SIZE> Permutation(NumRegisters);
if (Randomized) {
// Create a random number generator for regalloc randomization. Merge
// function's sequence and Kind value as the Salt. Because regAlloc() is
@@ -805,8 +792,8 @@ void LinearScan::assignFinalRegisters(
// Finish up by setting RegNum = RegNumTmp (or a random permutation thereof)
// for each Variable.
for (Variable *Item : Handled) {
- int32_t RegNum = Item->getRegNumTmp();
- int32_t AssignedRegNum = RegNum;
+ auto RegNum = Item->getRegNumTmp();
+ auto AssignedRegNum = RegNum;
if (Randomized && Item->hasRegTmp() && !Item->hasReg()) {
AssignedRegNum = Permutation[RegNum];
@@ -917,7 +904,7 @@ void LinearScan::scan(const llvm::SmallBitVector &RegMaskFull,
if (Iter.AllowOverlap) {
const llvm::SmallBitVector &Aliases = *RegAliases[Iter.PreferReg];
for (const Variable *Item : Active) {
- int32_t RegNum = Item->getRegNumTmp();
+ RegNumT RegNum = Item->getRegNumTmp();
if (Item != Iter.Prefer && Aliases[RegNum] &&
overlapsDefs(Func, Iter.Cur, Item)) {
Iter.AllowOverlap = false;
@@ -940,8 +927,7 @@ void LinearScan::scan(const llvm::SmallBitVector &RegMaskFull,
if (Iter.Cur->getLiveRange().overlaps(KillsRange, UseTrimmed)) {
Iter.Free.reset(KillsMask);
Iter.FreeUnfiltered.reset(KillsMask);
- for (int i = KillsMask.find_first(); i != -1;
- i = KillsMask.find_next(i)) {
+ for (RegNumT i : RegNumBitVector(KillsMask)) {
Iter.Weights[i].setWeight(RegWeight::Inf);
if (Iter.PreferReg == i)
Iter.AllowOverlap = false;
@@ -951,12 +937,10 @@ void LinearScan::scan(const llvm::SmallBitVector &RegMaskFull,
// Print info about physical register availability.
if (BuildDefs::dump() && Verbose) {
Ostream &Str = Ctx->getStrDump();
- for (SizeT i = 0; i < Iter.RegMask.size(); ++i) {
- if (Iter.RegMaskUnfiltered[i]) {
- Str << Target->getRegName(i, Iter.Cur->getType())
- << "(U=" << RegUses[i] << ",F=" << Iter.Free[i]
- << ",P=" << Iter.PrecoloredUnhandledMask[i] << ") ";
- }
+ for (RegNumT i : RegNumBitVector(Iter.RegMaskUnfiltered)) {
+ Str << Target->getRegName(i, Iter.Cur->getType()) << "(U=" << RegUses[i]
+ << ",F=" << Iter.Free[i] << ",P=" << Iter.PrecoloredUnhandledMask[i]
+ << ") ";
}
Str << "\n";
}
« src/IceOperand.h ('K') | « src/IceRegAlloc.h ('k') | src/IceRegistersARM32.h » ('j') | src/IceTargetLoweringX8664Traits.h » ('J')

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