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| 1 //===- subzero/src/IceDefs.h - Common Subzero declarations ------*- C++ -*-===// | 1 //===- subzero/src/IceDefs.h - Common Subzero declarations ------*- C++ -*-===// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 /// | 9 /// |
| 10 /// \file | 10 /// \file |
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| 175 | 175 |
| 176 /// SizeT is for holding small-ish limits like number of source operands in an | 176 /// SizeT is for holding small-ish limits like number of source operands in an |
| 177 /// instruction. It is used instead of size_t (which may be 64-bits wide) when | 177 /// instruction. It is used instead of size_t (which may be 64-bits wide) when |
| 178 /// we want to save space. | 178 /// we want to save space. |
| 179 using SizeT = uint32_t; | 179 using SizeT = uint32_t; |
| 180 | 180 |
| 181 /// InstNumberT is for holding an instruction number. Instruction numbers are | 181 /// InstNumberT is for holding an instruction number. Instruction numbers are |
| 182 /// used for representing Variable live ranges. | 182 /// used for representing Variable live ranges. |
| 183 using InstNumberT = int32_t; | 183 using InstNumberT = int32_t; |
| 184 | 184 |
| 185 /// RegNumT is for holding target-specific register numbers, plus the sentinel | |
| 186 /// value NoRegister. | |
| 187 class RegNumT { | |
| 188 public: | |
| 189 using BaseType = uint32_t; | |
| 190 // TODO(stichnot): This ctor is explicitly not "explicit". Find a way to make | |
| 191 // it explicit without imposing an undue burden on its users. | |
| 192 RegNumT(BaseType Value) : Value(Value) {} | |
|
Eric Holk
2016/02/08 19:37:09
Should this check that Value is a legal register v
Jim Stichnoth
2016/02/09 19:33:39
I don't really think it's possible to check for va
Eric Holk
2016/02/10 01:11:30
Hmm, good point. I guess you'd have to do somethin
| |
| 193 RegNumT() = default; | |
| 194 RegNumT(const RegNumT &) = default; | |
| 195 RegNumT &operator=(const RegNumT &) = default; | |
| 196 operator unsigned() const { return Value; } | |
| 197 /// Marks cases that inappropriately add/subtract RegNumT values, and | |
| 198 /// therefore need to be fixed because they make assumptions about register | |
| 199 /// enum value ordering. | |
| 200 static RegNumT fixme(BaseType Value) { return RegNumT(Value); } | |
|
Eric Holk
2016/02/08 19:37:09
Is the idea that eventually we won't do any conver
Jim Stichnoth
2016/02/09 19:33:39
Yes - added a TODO to remove the method when all u
Eric Holk
2016/02/10 01:11:30
Sounds good.
| |
| 201 static constexpr BaseType NoRegister = std::numeric_limits<BaseType>::max(); | |
| 202 | |
| 203 private: | |
| 204 BaseType Value = NoRegister; | |
| 205 /// Disallow operators that inappropriately make assumptions about register | |
| 206 /// enum value ordering. | |
| 207 bool operator<(const RegNumT &) = delete; | |
| 208 bool operator<=(const RegNumT &) = delete; | |
| 209 bool operator>(const RegNumT &) = delete; | |
| 210 bool operator>=(const RegNumT &) = delete; | |
| 211 }; | |
| 212 | |
| 185 /// A LiveBeginEndMapEntry maps a Variable::Number value to an Inst::Number | 213 /// A LiveBeginEndMapEntry maps a Variable::Number value to an Inst::Number |
| 186 /// value, giving the instruction number that begins or ends a variable's live | 214 /// value, giving the instruction number that begins or ends a variable's live |
| 187 /// range. | 215 /// range. |
| 188 using LiveBeginEndMapEntry = std::pair<SizeT, InstNumberT>; | 216 using LiveBeginEndMapEntry = std::pair<SizeT, InstNumberT>; |
| 189 using LiveBeginEndMap = CfgVector<LiveBeginEndMapEntry>; | 217 using LiveBeginEndMap = CfgVector<LiveBeginEndMapEntry>; |
| 190 using LivenessBV = llvm::BitVector; | 218 using LivenessBV = llvm::BitVector; |
| 191 | 219 |
| 192 using TimerStackIdT = uint32_t; | 220 using TimerStackIdT = uint32_t; |
| 193 using TimerIdT = uint32_t; | 221 using TimerIdT = uint32_t; |
| 194 | 222 |
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| 309 RPE_PooledConstantReordering, | 337 RPE_PooledConstantReordering, |
| 310 RPE_RegAllocRandomization, | 338 RPE_RegAllocRandomization, |
| 311 RPE_num | 339 RPE_num |
| 312 }; | 340 }; |
| 313 | 341 |
| 314 using RelocOffsetArray = llvm::SmallVector<class RelocOffset *, 4>; | 342 using RelocOffsetArray = llvm::SmallVector<class RelocOffset *, 4>; |
| 315 | 343 |
| 316 } // end of namespace Ice | 344 } // end of namespace Ice |
| 317 | 345 |
| 318 #endif // SUBZERO_SRC_ICEDEFS_H | 346 #endif // SUBZERO_SRC_ICEDEFS_H |
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