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1 //===- subzero/src/IceTargetLoweringMIPS32.h - MIPS32 lowering ---*- C++-*-===// | 1 //===- subzero/src/IceTargetLoweringMIPS32.h - MIPS32 lowering ---*- C++-*-===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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40 | 40 |
41 std::unique_ptr<::Ice::Assembler> createAssembler() const override { | 41 std::unique_ptr<::Ice::Assembler> createAssembler() const override { |
42 return makeUnique<MIPS32::AssemblerMIPS32>(); | 42 return makeUnique<MIPS32::AssemblerMIPS32>(); |
43 } | 43 } |
44 | 44 |
45 void translateOm1() override; | 45 void translateOm1() override; |
46 void translateO2() override; | 46 void translateO2() override; |
47 bool doBranchOpt(Inst *Instr, const CfgNode *NextNode) override; | 47 bool doBranchOpt(Inst *Instr, const CfgNode *NextNode) override; |
48 | 48 |
49 SizeT getNumRegisters() const override { return RegMIPS32::Reg_NUM; } | 49 SizeT getNumRegisters() const override { return RegMIPS32::Reg_NUM; } |
50 Variable *getPhysicalRegister(SizeT RegNum, Type Ty = IceType_void) override; | 50 Variable *getPhysicalRegister(RegNumT RegNum, |
51 IceString getRegName(SizeT RegNum, Type Ty) const override; | 51 Type Ty = IceType_void) override; |
| 52 IceString getRegName(RegNumT RegNum, Type Ty) const override; |
52 llvm::SmallBitVector getRegisterSet(RegSetMask Include, | 53 llvm::SmallBitVector getRegisterSet(RegSetMask Include, |
53 RegSetMask Exclude) const override; | 54 RegSetMask Exclude) const override; |
54 const llvm::SmallBitVector & | 55 const llvm::SmallBitVector & |
55 getRegistersForVariable(const Variable *Var) const override { | 56 getRegistersForVariable(const Variable *Var) const override { |
56 RegClass RC = Var->getRegClass(); | 57 RegClass RC = Var->getRegClass(); |
57 assert(RC < RC_Target); | 58 assert(RC < RC_Target); |
58 return TypeToRegisterSet[RC]; | 59 return TypeToRegisterSet[RC]; |
59 } | 60 } |
60 const llvm::SmallBitVector & | 61 const llvm::SmallBitVector & |
61 getAllRegistersForVariable(const Variable *Var) const override { | 62 getAllRegistersForVariable(const Variable *Var) const override { |
62 RegClass RC = Var->getRegClass(); | 63 RegClass RC = Var->getRegClass(); |
63 assert(RC < RC_Target); | 64 assert(RC < RC_Target); |
64 return TypeToRegisterSetUnfiltered[RC]; | 65 return TypeToRegisterSetUnfiltered[RC]; |
65 } | 66 } |
66 const llvm::SmallBitVector &getAliasesForRegister(SizeT Reg) const override { | 67 const llvm::SmallBitVector & |
| 68 getAliasesForRegister(RegNumT Reg) const override { |
67 return RegisterAliases[Reg]; | 69 return RegisterAliases[Reg]; |
68 } | 70 } |
69 bool hasFramePointer() const override { return UsesFramePointer; } | 71 bool hasFramePointer() const override { return UsesFramePointer; } |
70 void setHasFramePointer() override { UsesFramePointer = true; } | 72 void setHasFramePointer() override { UsesFramePointer = true; } |
71 SizeT getStackReg() const override { return RegMIPS32::Reg_SP; } | 73 RegNumT getStackReg() const override { return RegMIPS32::Reg_SP; } |
72 SizeT getFrameReg() const override { return RegMIPS32::Reg_FP; } | 74 RegNumT getFrameReg() const override { return RegMIPS32::Reg_FP; } |
73 SizeT getFrameOrStackReg() const override { | 75 RegNumT getFrameOrStackReg() const override { |
74 return UsesFramePointer ? getFrameReg() : getStackReg(); | 76 return UsesFramePointer ? getFrameReg() : getStackReg(); |
75 } | 77 } |
76 size_t typeWidthInBytesOnStack(Type Ty) const override { | 78 size_t typeWidthInBytesOnStack(Type Ty) const override { |
77 // Round up to the next multiple of 4 bytes. In particular, i1, i8, and i16 | 79 // Round up to the next multiple of 4 bytes. In particular, i1, i8, and i16 |
78 // are rounded up to 4 bytes. | 80 // are rounded up to 4 bytes. |
79 return (typeWidthInBytes(Ty) + 3) & ~3; | 81 return (typeWidthInBytes(Ty) + 3) & ~3; |
80 } | 82 } |
81 uint32_t getStackAlignment() const override { | 83 uint32_t getStackAlignment() const override { |
82 // TODO(sehr): what is the stack alignment? | 84 // TODO(sehr): what is the stack alignment? |
83 return 1; | 85 return 1; |
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211 /// without creating any new instructions or operands. | 213 /// without creating any new instructions or operands. |
212 enum OperandLegalization { | 214 enum OperandLegalization { |
213 Legal_None = 0, | 215 Legal_None = 0, |
214 Legal_Reg = 1 << 0, // physical register, not stack location | 216 Legal_Reg = 1 << 0, // physical register, not stack location |
215 Legal_Imm = 1 << 1, | 217 Legal_Imm = 1 << 1, |
216 Legal_Mem = 1 << 2, | 218 Legal_Mem = 1 << 2, |
217 Legal_Default = ~Legal_None | 219 Legal_Default = ~Legal_None |
218 }; | 220 }; |
219 typedef uint32_t LegalMask; | 221 typedef uint32_t LegalMask; |
220 Operand *legalize(Operand *From, LegalMask Allowed = Legal_Default, | 222 Operand *legalize(Operand *From, LegalMask Allowed = Legal_Default, |
221 int32_t RegNum = Variable::NoRegister); | 223 RegNumT RegNum = RegNumT::NoRegister); |
222 | 224 |
223 Variable *legalizeToVar(Operand *From, int32_t RegNum = Variable::NoRegister); | 225 Variable *legalizeToVar(Operand *From, RegNumT RegNum = RegNumT::NoRegister); |
224 | 226 |
225 Variable *legalizeToReg(Operand *From, int32_t RegNum = Variable::NoRegister); | 227 Variable *legalizeToReg(Operand *From, RegNumT RegNum = RegNumT::NoRegister); |
226 | 228 |
227 Variable *makeReg(Type Ty, int32_t RegNum = Variable::NoRegister); | 229 Variable *makeReg(Type Ty, RegNumT RegNum = RegNumT::NoRegister); |
228 static Type stackSlotType(); | 230 static Type stackSlotType(); |
229 Variable *copyToReg(Operand *Src, int32_t RegNum = Variable::NoRegister); | 231 Variable *copyToReg(Operand *Src, RegNumT RegNum = RegNumT::NoRegister); |
230 | 232 |
231 void addProlog(CfgNode *Node) override; | 233 void addProlog(CfgNode *Node) override; |
232 void addEpilog(CfgNode *Node) override; | 234 void addEpilog(CfgNode *Node) override; |
233 | 235 |
234 // Ensure that a 64-bit Variable has been split into 2 32-bit | 236 // Ensure that a 64-bit Variable has been split into 2 32-bit |
235 // Variables, creating them if necessary. This is needed for all | 237 // Variables, creating them if necessary. This is needed for all |
236 // I64 operations. | 238 // I64 operations. |
237 void split64(Variable *Var); | 239 void split64(Variable *Var); |
238 Operand *loOperand(Operand *Operand); | 240 Operand *loOperand(Operand *Operand); |
239 Operand *hiOperand(Operand *Operand); | 241 Operand *hiOperand(Operand *Operand); |
240 | 242 |
241 Operand *legalizeUndef(Operand *From, int32_t RegNum = Variable::NoRegister); | 243 Operand *legalizeUndef(Operand *From, RegNumT RegNum = RegNumT::NoRegister); |
242 | 244 |
243 protected: | 245 protected: |
244 explicit TargetMIPS32(Cfg *Func); | 246 explicit TargetMIPS32(Cfg *Func); |
245 | 247 |
246 void postLower() override; | 248 void postLower() override; |
247 | 249 |
248 void lowerAlloca(const InstAlloca *Instr) override; | 250 void lowerAlloca(const InstAlloca *Instr) override; |
249 void lowerArithmetic(const InstArithmetic *Instr) override; | 251 void lowerArithmetic(const InstArithmetic *Instr) override; |
250 void lowerInt64Arithmetic(const InstArithmetic *Instr, Variable *Dest, | 252 void lowerInt64Arithmetic(const InstArithmetic *Instr, Variable *Dest, |
251 Operand *Src0, Operand *Src1); | 253 Operand *Src0, Operand *Src1); |
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269 uint32_t getCallStackArgumentsSizeBytes(const InstCall *Instr) override { | 271 uint32_t getCallStackArgumentsSizeBytes(const InstCall *Instr) override { |
270 (void)Instr; | 272 (void)Instr; |
271 return 0; | 273 return 0; |
272 } | 274 } |
273 void genTargetHelperCallFor(Inst *Instr) override { (void)Instr; } | 275 void genTargetHelperCallFor(Inst *Instr) override { (void)Instr; } |
274 void doAddressOptLoad() override; | 276 void doAddressOptLoad() override; |
275 void doAddressOptStore() override; | 277 void doAddressOptStore() override; |
276 void randomlyInsertNop(float Probability, | 278 void randomlyInsertNop(float Probability, |
277 RandomNumberGenerator &RNG) override; | 279 RandomNumberGenerator &RNG) override; |
278 void | 280 void |
279 makeRandomRegisterPermutation(llvm::SmallVectorImpl<int32_t> &Permutation, | 281 makeRandomRegisterPermutation(llvm::SmallVectorImpl<RegNumT> &Permutation, |
280 const llvm::SmallBitVector &ExcludeRegisters, | 282 const llvm::SmallBitVector &ExcludeRegisters, |
281 uint64_t Salt) const override; | 283 uint64_t Salt) const override; |
282 | 284 |
283 bool UsesFramePointer = false; | 285 bool UsesFramePointer = false; |
284 bool NeedsStackAlignment = false; | 286 bool NeedsStackAlignment = false; |
285 static llvm::SmallBitVector TypeToRegisterSet[RCMIPS32_NUM]; | 287 static llvm::SmallBitVector TypeToRegisterSet[RCMIPS32_NUM]; |
286 static llvm::SmallBitVector TypeToRegisterSetUnfiltered[RCMIPS32_NUM]; | 288 static llvm::SmallBitVector TypeToRegisterSetUnfiltered[RCMIPS32_NUM]; |
287 static llvm::SmallBitVector RegisterAliases[RegMIPS32::Reg_NUM]; | 289 static llvm::SmallBitVector RegisterAliases[RegMIPS32::Reg_NUM]; |
288 llvm::SmallBitVector RegsUsed; | 290 llvm::SmallBitVector RegsUsed; |
289 VarList PhysicalRegisters[IceType_NUM]; | 291 VarList PhysicalRegisters[IceType_NUM]; |
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331 explicit TargetHeaderMIPS32(GlobalContext *Ctx); | 333 explicit TargetHeaderMIPS32(GlobalContext *Ctx); |
332 | 334 |
333 private: | 335 private: |
334 ~TargetHeaderMIPS32() = default; | 336 ~TargetHeaderMIPS32() = default; |
335 }; | 337 }; |
336 | 338 |
337 } // end of namespace MIPS32 | 339 } // end of namespace MIPS32 |
338 } // end of namespace Ice | 340 } // end of namespace Ice |
339 | 341 |
340 #endif // SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H | 342 #endif // SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H |
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