Subzero: Use a proper RegNumT type instead of int32_t/SizeT.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 215 matching lines @@
 }
 
 namespace {
 constexpr SizeT NumGPRArgs =
 #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,   \
           isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)       \
   +(((cc_arg) > 0) ? 1 : 0)
     REGARM32_GPR_TABLE
 #undef X
     ;
-std::array<uint32_t, NumGPRArgs> GPRArgInitializer;
+std::array<RegNumT, NumGPRArgs> GPRArgInitializer;
 
 constexpr SizeT NumI64Args =
 #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,   \
           isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)       \
   +(((cc_arg) > 0) ? 1 : 0)
     REGARM32_I64PAIR_TABLE
 #undef X
     ;
-std::array<uint32_t, NumI64Args> I64ArgInitializer;
+std::array<RegNumT, NumI64Args> I64ArgInitializer;
 
 constexpr SizeT NumFP32Args =
 #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,   \
           isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)       \
   +(((cc_arg) > 0) ? 1 : 0)
     REGARM32_FP32_TABLE
 #undef X
     ;
-std::array<uint32_t, NumFP32Args> FP32ArgInitializer;
+std::array<RegNumT, NumFP32Args> FP32ArgInitializer;
 
 constexpr SizeT NumFP64Args =
 #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,   \
           isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)       \
   +(((cc_arg) > 0) ? 1 : 0)
     REGARM32_FP64_TABLE
 #undef X
     ;
-std::array<uint32_t, NumFP64Args> FP64ArgInitializer;
+std::array<RegNumT, NumFP64Args> FP64ArgInitializer;
 
 constexpr SizeT NumVec128Args =
 #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,   \
           isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)       \
   +(((cc_arg > 0)) ? 1 : 0)
     REGARM32_VEC128_TABLE
 #undef X
     ;
-std::array<uint32_t, NumVec128Args> Vec128ArgInitializer;
+std::array<RegNumT, NumVec128Args> Vec128ArgInitializer;
 
 IceString getRegClassName(RegClass C) {
   auto ClassNum = static_cast<RegARM32::RegClassARM32>(C);
   assert(ClassNum < RegARM32::RCARM32_NUM);
   switch (ClassNum) {
   default:
     assert(C < RC_Target);
     return regClassString(C);
     // Add handling of new register classes below.
   }
 }
 
 } // end of anonymous namespace
 
 TargetARM32::TargetARM32(Cfg *Func)
     : TargetLowering(Func), NeedSandboxing(SandboxingType == ST_NaCl),
       CPUFeatures(Func->getContext()->getFlags()) {}
 
 void TargetARM32::staticInit(GlobalContext *Ctx) {
-
+  RegNumT::setLimit(RegARM32::Reg_NUM);
   // Limit this size (or do all bitsets need to be the same width)???
   llvm::SmallBitVector IntegerRegisters(RegARM32::Reg_NUM);
   llvm::SmallBitVector I64PairRegisters(RegARM32::Reg_NUM);
   llvm::SmallBitVector Float32Registers(RegARM32::Reg_NUM);
   llvm::SmallBitVector Float64Registers(RegARM32::Reg_NUM);
   llvm::SmallBitVector VectorRegisters(RegARM32::Reg_NUM);
   llvm::SmallBitVector QtoSRegisters(RegARM32::Reg_NUM);
   llvm::SmallBitVector InvalidRegisters(RegARM32::Reg_NUM);
   const unsigned EncodedReg_q8 = RegARM32::RegTable[RegARM32::Reg_q8].Encoding;
   for (int i = 0; i < RegARM32::Reg_NUM; ++i) {
     const auto &Entry = RegARM32::RegTable[i];
     IntegerRegisters[i] = Entry.IsInt;
     I64PairRegisters[i] = Entry.IsI64Pair;
     Float32Registers[i] = Entry.IsFP32;
     Float64Registers[i] = Entry.IsFP64;
     VectorRegisters[i] = Entry.IsVec128;
     RegisterAliases[i].resize(RegARM32::Reg_NUM);
     // TODO(eholk): It would be better to store a QtoS flag in the
     // IceRegistersARM32 table than to compare their encodings here.
     QtoSRegisters[i] = Entry.IsVec128 && Entry.Encoding < EncodedReg_q8;
     for (int j = 0; j < Entry.NumAliases; ++j) {
       assert(i == j || !RegisterAliases[i][Entry.Aliases[j]]);
       RegisterAliases[i].set(Entry.Aliases[j]);
     }
     assert(RegisterAliases[i][i]);
     if (Entry.CCArg <= 0) {
       continue;
     }
+    const auto RegNum = RegNumT::fromInt(i);
     if (Entry.IsGPR) {
-      GPRArgInitializer[Entry.CCArg - 1] = i;
+      GPRArgInitializer[Entry.CCArg - 1] = RegNum;
     } else if (Entry.IsI64Pair) {
-      I64ArgInitializer[Entry.CCArg - 1] = i;
+      I64ArgInitializer[Entry.CCArg - 1] = RegNum;
     } else if (Entry.IsFP32) {
-      FP32ArgInitializer[Entry.CCArg - 1] = i;
+      FP32ArgInitializer[Entry.CCArg - 1] = RegNum;
     } else if (Entry.IsFP64) {
-      FP64ArgInitializer[Entry.CCArg - 1] = i;
+      FP64ArgInitializer[Entry.CCArg - 1] = RegNum;
     } else if (Entry.IsVec128) {
-      Vec128ArgInitializer[Entry.CCArg - 1] = i;
+      Vec128ArgInitializer[Entry.CCArg - 1] = RegNum;
     }
   }
   TypeToRegisterSet[IceType_void] = InvalidRegisters;
   TypeToRegisterSet[IceType_i1] = IntegerRegisters;
   TypeToRegisterSet[IceType_i8] = IntegerRegisters;
   TypeToRegisterSet[IceType_i16] = IntegerRegisters;
   TypeToRegisterSet[IceType_i32] = IntegerRegisters;
   TypeToRegisterSet[IceType_i64] = I64PairRegisters;
   TypeToRegisterSet[IceType_f32] = Float32Registers;
   TypeToRegisterSet[IceType_f64] = Float64Registers;
   TypeToRegisterSet[IceType_v4i1] = VectorRegisters;
   TypeToRegisterSet[IceType_v8i1] = VectorRegisters;
   TypeToRegisterSet[IceType_v16i1] = VectorRegisters;
   TypeToRegisterSet[IceType_v16i8] = VectorRegisters;
   TypeToRegisterSet[IceType_v8i16] = VectorRegisters;
   TypeToRegisterSet[IceType_v4i32] = VectorRegisters;
   TypeToRegisterSet[IceType_v4f32] = VectorRegisters;
   TypeToRegisterSet[RegARM32::RCARM32_QtoS] = QtoSRegisters;
 
   for (size_t i = 0; i < llvm::array_lengthof(TypeToRegisterSet); ++i)
     TypeToRegisterSetUnfiltered[i] = TypeToRegisterSet[i];
 
   filterTypeToRegisterSet(
       Ctx, RegARM32::Reg_NUM, TypeToRegisterSet,
-      llvm::array_lengthof(TypeToRegisterSet), [](int32_t RegNum) -> IceString {
+      llvm::array_lengthof(TypeToRegisterSet), [](RegNumT RegNum) -> IceString {
         // This function simply removes ", " from the register name.
         IceString Name = RegARM32::getRegName(RegNum);
         constexpr const char RegSeparator[] = ", ";
         constexpr size_t RegSeparatorWidth =
             llvm::array_lengthof(RegSeparator) - 1;
         for (size_t Pos = Name.find(RegSeparator); Pos != std::string::npos;
              Pos = Name.find(RegSeparator)) {
           Name.replace(Pos, RegSeparatorWidth, "");
         }
         return Name;
       }, getRegClassName);
 }
 
 namespace {
 void copyRegAllocFromInfWeightVariable64On32(const VarList &Vars) {
   for (Variable *Var : Vars) {
     auto *Var64 = llvm::dyn_cast<Variable64On32>(Var);
     if (!Var64) {
       // This is not the variable we are looking for.
       continue;
     }
     assert(Var64->hasReg() || !Var64->mustHaveReg());
     if (!Var64->hasReg()) {
       continue;
     }
-    SizeT FirstReg = RegARM32::getI64PairFirstGPRNum(Var->getRegNum());
+    const auto FirstReg =
+        RegNumT::fixme(RegARM32::getI64PairFirstGPRNum(Var->getRegNum()));
     // This assumes little endian.
     Variable *Lo = Var64->getLo();
     Variable *Hi = Var64->getHi();
     assert(Lo->hasReg() == Hi->hasReg());
     if (Lo->hasReg()) {
       continue;
     }
     Lo->setRegNum(FirstReg);
     Lo->setMustHaveReg();
-    Hi->setRegNum(FirstReg + 1);
+    Hi->setRegNum(RegNumT::fixme(FirstReg + 1));
     Hi->setMustHaveReg();
   }
 }
 } // end of anonymous namespace
 
 uint32_t TargetARM32::getCallStackArgumentsSizeBytes(const InstCall *Call) {
   TargetARM32::CallingConv CC;
-  int32_t DummyReg;
+  RegNumT DummyReg;
   size_t OutArgsSizeBytes = 0;
   for (SizeT i = 0, NumArgs = Call->getNumArgs(); i < NumArgs; ++i) {
     Operand *Arg = legalizeUndef(Call->getArg(i));
     const Type Ty = Arg->getType();
     if (isScalarIntegerType(Ty)) {
       if (CC.argInGPR(Ty, &DummyReg)) {
         continue;
       }
     } else {
       if (CC.argInVFP(Ty, &DummyReg)) {
@@ skipping 503 matching lines @@
   return ARM32_STACK_ALIGNMENT_BYTES;
 }
 
 bool TargetARM32::doBranchOpt(Inst *I, const CfgNode *NextNode) {
   if (auto *Br = llvm::dyn_cast<InstARM32Br>(I)) {
     return Br->optimizeBranch(NextNode);
   }
   return false;
 }
 
-IceString TargetARM32::getRegName(SizeT RegNum, Type Ty) const {
-  assert(RegNum < RegARM32::Reg_NUM);
+IceString TargetARM32::getRegName(RegNumT RegNum, Type Ty) const {
   (void)Ty;
   return RegARM32::getRegName(RegNum);
 }
 
-Variable *TargetARM32::getPhysicalRegister(SizeT RegNum, Type Ty) {
+Variable *TargetARM32::getPhysicalRegister(RegNumT RegNum, Type Ty) {
   static const Type DefaultType[] = {
 #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,   \
           isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)       \
   (isFP32)                                                                     \
       ? IceType_f32                                                            \
       : ((isFP64) ? IceType_f64 : ((isVec128 ? IceType_v4i32 : IceType_i32))),
       REGARM32_TABLE
 #undef X
   };
 
-  assert(RegNum < RegARM32::Reg_NUM);
   if (Ty == IceType_void) {
-    assert(RegNum < llvm::array_lengthof(DefaultType));
+    assert(unsigned(RegNum) < llvm::array_lengthof(DefaultType));
     Ty = DefaultType[RegNum];
   }
   if (PhysicalRegisters[Ty].empty())
     PhysicalRegisters[Ty].resize(RegARM32::Reg_NUM);
-  assert(RegNum < PhysicalRegisters[Ty].size());
+  assert(unsigned(RegNum) < PhysicalRegisters[Ty].size());
   Variable *Reg = PhysicalRegisters[Ty][RegNum];
   if (Reg == nullptr) {
     Reg = Func->makeVariable(Ty);
     Reg->setRegNum(RegNum);
     PhysicalRegisters[Ty][RegNum] = Reg;
     // Specially mark a named physical register as an "argument" so that it is
     // considered live upon function entry.  Otherwise it's possible to get
     // liveness validation errors for saving callee-save registers.
     Func->addImplicitArg(Reg);
     // Don't bother tracking the live range of a named physical register.
@@ skipping 16 matching lines @@
     Str << getRegName(Var->getRegNum(), Var->getType());
     return;
   }
   if (Var->mustHaveReg()) {
     llvm::report_fatal_error("Infinite-weight Variable (" + Var->getName(Func) +
                              ") has no register assigned - function " +
                              Func->getFunctionName());
   }
   assert(!Var->isRematerializable());
   int32_t Offset = Var->getStackOffset();
-  int32_t BaseRegNum = Var->getBaseRegNum();
-  if (BaseRegNum == Variable::NoRegister) {
+  auto BaseRegNum = Var->getBaseRegNum();
+  if (BaseRegNum == RegNumT::NoRegister) {
     BaseRegNum = getFrameOrStackReg();
   }
   const Type VarTy = Var->getType();
   Str << "[" << getRegName(BaseRegNum, VarTy);
   if (Offset != 0) {
     Str << ", #" << Offset;
   }
   Str << "]";
 }
 
 TargetARM32::CallingConv::CallingConv()
     : GPRegsUsed(RegARM32::Reg_NUM),
       GPRArgs(GPRArgInitializer.rbegin(), GPRArgInitializer.rend()),
       I64Args(I64ArgInitializer.rbegin(), I64ArgInitializer.rend()),
       VFPRegsUsed(RegARM32::Reg_NUM),
       FP32Args(FP32ArgInitializer.rbegin(), FP32ArgInitializer.rend()),
       FP64Args(FP64ArgInitializer.rbegin(), FP64ArgInitializer.rend()),
       Vec128Args(Vec128ArgInitializer.rbegin(), Vec128ArgInitializer.rend()) {}
 
-bool TargetARM32::CallingConv::argInGPR(Type Ty, int32_t *Reg) {
-  CfgVector<SizeT> *Source;
+bool TargetARM32::CallingConv::argInGPR(Type Ty, RegNumT *Reg) {
+  CfgVector<RegNumT> *Source;
 
   switch (Ty) {
   default: {
     assert(isScalarIntegerType(Ty));
     Source = &GPRArgs;
   } break;
   case IceType_i64: {
     Source = &I64Args;
   } break;
   }
@@ skipping 13 matching lines @@
   GPRegsUsed |= RegisterAliases[*Reg];
   return true;
 }
 
 // GPR are not packed when passing parameters. Thus, a function foo(i32, i64,
 // i32) will have the first argument in r0, the second in r1-r2, and the third
 // on the stack. To model this behavior, whenever we pop a register from Regs,
 // we remove all of its aliases from the pool of available GPRs. This has the
 // effect of computing the "closure" on the GPR registers.
 void TargetARM32::CallingConv::discardUnavailableGPRsAndTheirAliases(
-    CfgVector<SizeT> *Regs) {
+    CfgVector<RegNumT> *Regs) {
   while (!Regs->empty() && GPRegsUsed[Regs->back()]) {
     GPRegsUsed |= RegisterAliases[Regs->back()];
     Regs->pop_back();
   }
 }
 
-bool TargetARM32::CallingConv::argInVFP(Type Ty, int32_t *Reg) {
-  CfgVector<SizeT> *Source;
+bool TargetARM32::CallingConv::argInVFP(Type Ty, RegNumT *Reg) {
+  CfgVector<RegNumT> *Source;
 
   switch (Ty) {
   default: {
     assert(isVectorType(Ty));
     Source = &Vec128Args;
   } break;
   case IceType_f32: {
     Source = &FP32Args;
   } break;
   case IceType_f64: {
     Source = &FP64Args;
   } break;
   }
 
   discardUnavailableVFPRegs(Source);
 
   if (Source->empty()) {
     VFPRegsUsed.set();
     return false;
   }
 
   *Reg = Source->back();
   VFPRegsUsed |= RegisterAliases[*Reg];
   return true;
 }
 
 // Arguments in VFP registers are not packed, so we don't mark the popped
 // registers' aliases as unavailable.
 void TargetARM32::CallingConv::discardUnavailableVFPRegs(
-    CfgVector<SizeT> *Regs) {
+    CfgVector<RegNumT> *Regs) {
   while (!Regs->empty() && VFPRegsUsed[Regs->back()]) {
     Regs->pop_back();
   }
 }
 
 void TargetARM32::lowerArguments() {
   VarList &Args = Func->getArgs();
   TargetARM32::CallingConv CC;
 
   // For each register argument, replace Arg in the argument list with the home
   // register. Then generate an instruction in the prolog to copy the home
   // register to the assigned location of Arg.
   Context.init(Func->getEntryNode());
   Context.setInsertPoint(Context.getCur());
 
   for (SizeT I = 0, E = Args.size(); I < E; ++I) {
     Variable *Arg = Args[I];
     Type Ty = Arg->getType();
-    int RegNum;
+    RegNumT RegNum;
     if (isScalarIntegerType(Ty)) {
       if (!CC.argInGPR(Ty, &RegNum)) {
         continue;
       }
     } else {
       if (!CC.argInVFP(Ty, &RegNum)) {
         continue;
       }
     }
 
     Variable *RegisterArg = Func->makeVariable(Ty);
     if (BuildDefs::dump()) {
       RegisterArg->setName(Func, "home_reg:" + Arg->getName(Func));
     }
     RegisterArg->setIsArg();
     Arg->setIsArg(false);
     Args[I] = RegisterArg;
     switch (Ty) {
     default: { RegisterArg->setRegNum(RegNum); } break;
     case IceType_i64: {
       auto *RegisterArg64 = llvm::cast<Variable64On32>(RegisterArg);
       RegisterArg64->initHiLo(Func);
       RegisterArg64->getLo()->setRegNum(
-          RegARM32::getI64PairFirstGPRNum(RegNum));
+          RegNumT::fixme(RegARM32::getI64PairFirstGPRNum(RegNum)));
       RegisterArg64->getHi()->setRegNum(
-          RegARM32::getI64PairSecondGPRNum(RegNum));
+          RegNumT::fixme(RegARM32::getI64PairSecondGPRNum(RegNum)));
     } break;
     }
     Context.insert<InstAssign>(Arg, RegisterArg);
   }
 }
 
 // Helper function for addProlog().
 //
 // This assumes Arg is an argument passed on the stack. This sets the frame
 // offset for Arg and updates InArgsSizeBytes according to Arg's width. For an
@@ skipping 164 matching lines @@
                    &PreservedSRegs)};
   for (const auto &RegClass : RegClasses) {
     const uint32_t FirstRegInClass = std::get<0>(RegClass);
     const uint32_t LastRegInClass = std::get<1>(RegClass);
     VarList *const PreservedRegsInClass = std::get<2>(RegClass);
     for (uint32_t Reg = FirstRegInClass; Reg <= LastRegInClass; ++Reg) {
       if (!ToPreserve[Reg]) {
         continue;
       }
       ++NumCallee;
-      Variable *PhysicalRegister = getPhysicalRegister(Reg);
+      Variable *PhysicalRegister = getPhysicalRegister(RegNumT::fromInt(Reg));
       PreservedRegsSizeBytes +=
           typeWidthInBytesOnStack(PhysicalRegister->getType());
       PreservedRegsInClass->push_back(PhysicalRegister);
     }
   }
 
   Ctx->statsUpdateRegistersSaved(NumCallee);
   if (!PreservedSRegs.empty())
     _push(PreservedSRegs);
   if (!PreservedGPRs.empty())
@@ skipping 54 matching lines @@
   // Arg[0] is closest to the stack/frame pointer.
   Variable *FramePtr = getPhysicalRegister(getFrameOrStackReg());
   size_t BasicFrameOffset = PreservedRegsSizeBytes;
   if (!UsesFramePointer)
     BasicFrameOffset += SpillAreaSizeBytes;
 
   const VarList &Args = Func->getArgs();
   size_t InArgsSizeBytes = 0;
   TargetARM32::CallingConv CC;
   for (Variable *Arg : Args) {
-    int32_t DummyReg;
+    RegNumT DummyReg;
     const Type Ty = Arg->getType();
 
     // Skip arguments passed in registers.
     if (isScalarIntegerType(Ty)) {
       if (CC.argInGPR(Ty, &DummyReg)) {
         continue;
       }
     } else {
       if (CC.argInVFP(Ty, &DummyReg)) {
         continue;
@@ skipping 98 matching lines @@
 
   RI->setDeleted();
 }
 
 bool TargetARM32::isLegalMemOffset(Type Ty, int32_t Offset) const {
   constexpr bool ZeroExt = false;
   return OperandARM32Mem::canHoldOffset(Ty, ZeroExt, Offset);
 }
 
 Variable *TargetARM32::PostLoweringLegalizer::newBaseRegister(
-    Variable *Base, int32_t Offset, int32_t ScratchRegNum) {
+    Variable *Base, int32_t Offset, RegNumT ScratchRegNum) {
   // Legalize will likely need a movw/movt combination, but if the top bits are
   // all 0 from negating the offset and subtracting, we could use that instead.
   const bool ShouldSub = Offset != 0 && (-Offset & 0xFFFF0000) == 0;
   Variable *ScratchReg = Target->makeReg(IceType_i32, ScratchRegNum);
   if (ShouldSub) {
     Operand *OffsetVal =
         Target->legalize(Target->Ctx->getConstantInt32(-Offset),
                          Legal_Reg | Legal_Flex, ScratchRegNum);
     Target->_sub(ScratchReg, Base, OffsetVal);
   } else {
     Operand *OffsetVal =
         Target->legalize(Target->Ctx->getConstantInt32(Offset),
                          Legal_Reg | Legal_Flex, ScratchRegNum);
     Target->_add(ScratchReg, Base, OffsetVal);
   }
 
   if (ScratchRegNum == Target->getReservedTmpReg()) {
     const bool BaseIsStackOrFramePtr =
-        Base->getRegNum() == static_cast<int32_t>(Target->getFrameOrStackReg());
+        Base->getRegNum() == Target->getFrameOrStackReg();
     // There is currently no code path that would trigger this assertion, so we
     // leave this assertion here in case it is ever violated. This is not a
     // fatal error (thus the use of assert() and not llvm::report_fatal_error)
     // as the program compiled by subzero will still work correctly.
     assert(BaseIsStackOrFramePtr);
     // Side-effect: updates TempBase to reflect the new Temporary.
     if (BaseIsStackOrFramePtr) {
       TempBaseReg = ScratchReg;
       TempBaseOffset = Offset;
     } else {
@@ skipping 86 matching lines @@
              MovInstr->getPredicate());
     // _str() does not have a Dest, so we add a fake-def(Dest).
     Target->Context.insert<InstFakeDef>(Dest);
     Legalized = true;
   } else if (auto *Var = llvm::dyn_cast<Variable>(Src)) {
     if (Var->isRematerializable()) {
       // This is equivalent to an x86 _lea(RematOffset(%esp/%ebp), Variable).
 
       // ExtraOffset is only needed for frame-pointer based frames as we have
       // to account for spill storage.
-      const int32_t ExtraOffset =
-          (static_cast<SizeT>(Var->getRegNum()) == Target->getFrameReg())
-              ? Target->getFrameFixedAllocaOffset()
-              : 0;
+      const int32_t ExtraOffset = (Var->getRegNum() == Target->getFrameReg())
+                                      ? Target->getFrameFixedAllocaOffset()
+                                      : 0;
 
       const int32_t Offset = Var->getStackOffset() + ExtraOffset;
       Variable *Base = Target->getPhysicalRegister(Var->getRegNum());
       Variable *T = newBaseRegister(Base, Offset, Dest->getRegNum());
       Target->_mov(Dest, T);
       Legalized = true;
     } else {
       if (!Var->hasReg()) {
         // This is a _mov(Variable, Mem()), i.e., a load.
         const int32_t Offset = Var->getStackOffset();
@@ skipping 47 matching lines @@
                                                        bool AllowOffsets) {
   assert(!Mem->isRegReg() || !Mem->getIndex()->isRematerializable());
   assert(
       Mem->isRegReg() ||
       Target->isLegalMemOffset(Mem->getType(), Mem->getOffset()->getValue()));
 
   bool Legalized = false;
   Variable *Base = Mem->getBase();
   int32_t Offset = Mem->isRegReg() ? 0 : Mem->getOffset()->getValue();
   if (Base->isRematerializable()) {
-    const int32_t ExtraOffset =
-        (static_cast<SizeT>(Base->getRegNum()) == Target->getFrameReg())
-            ? Target->getFrameFixedAllocaOffset()
-            : 0;
+    const int32_t ExtraOffset = (Base->getRegNum() == Target->getFrameReg())
+                                    ? Target->getFrameFixedAllocaOffset()
+                                    : 0;
     Offset += Base->getStackOffset() + ExtraOffset;
     Base = Target->getPhysicalRegister(Base->getRegNum());
     assert(!Base->isRematerializable());
     Legalized = true;
   }
 
   if (!Legalized && !Target->NeedSandboxing) {
     return nullptr;
   }
 
@@ skipping 199 matching lines @@
     }
   }
   llvm::report_fatal_error("Unsupported operand type");
   return nullptr;
 }
 
 llvm::SmallBitVector TargetARM32::getRegisterSet(RegSetMask Include,
                                                  RegSetMask Exclude) const {
   llvm::SmallBitVector Registers(RegARM32::Reg_NUM);
 
-  for (int32_t i = 0; i < RegARM32::Reg_NUM; ++i) {
+  for (uint32_t i = 0; i < RegARM32::Reg_NUM; ++i) {
     const auto &Entry = RegARM32::RegTable[i];
     if (Entry.Scratch && (Include & RegSet_CallerSave))
       Registers[i] = true;
     if (Entry.Preserved && (Include & RegSet_CalleeSave))
       Registers[i] = true;
     if (Entry.StackPtr && (Include & RegSet_StackPointer))
       Registers[i] = true;
     if (Entry.FramePtr && (Include & RegSet_FramePointer))
       Registers[i] = true;
     if (Entry.Scratch && (Exclude & RegSet_CallerSave))
@@ skipping 1443 matching lines @@
     if (TargetHelperPreamble != ARM32HelpersPreamble.end()) {
       (this->*TargetHelperPreamble->second)(Instr);
     }
   }
   MaybeLeafFunc = false;
   NeedsStackAlignment = true;
 
   // Assign arguments to registers and stack. Also reserve stack.
   TargetARM32::CallingConv CC;
   // Pair of Arg Operand -> GPR number assignments.
-  llvm::SmallVector<std::pair<Operand *, int32_t>, NumGPRArgs> GPRArgs;
-  llvm::SmallVector<std::pair<Operand *, int32_t>, NumFP32Args> FPArgs;
+  llvm::SmallVector<std::pair<Operand *, RegNumT>, NumGPRArgs> GPRArgs;
+  llvm::SmallVector<std::pair<Operand *, RegNumT>, NumFP32Args> FPArgs;
   // Pair of Arg Operand -> stack offset.
   llvm::SmallVector<std::pair<Operand *, int32_t>, 8> StackArgs;
   size_t ParameterAreaSizeBytes = 0;
 
   // Classify each argument operand according to the location where the
   // argument is passed.
   for (SizeT i = 0, NumArgs = Instr->getNumArgs(); i < NumArgs; ++i) {
     Operand *Arg = legalizeUndef(Instr->getArg(i));
     const Type Ty = Arg->getType();
     bool InReg = false;
-    int32_t Reg;
+    RegNumT Reg;
     if (isScalarIntegerType(Ty)) {
       InReg = CC.argInGPR(Ty, &Reg);
     } else {
       InReg = CC.argInVFP(Ty, &Reg);
     }
 
     if (!InReg) {
       ParameterAreaSizeBytes =
           applyStackAlignmentTy(ParameterAreaSizeBytes, Ty);
       StackArgs.push_back(std::make_pair(Arg, ParameterAreaSizeBytes));
       ParameterAreaSizeBytes += typeWidthInBytesOnStack(Ty);
       continue;
     }
 
     if (Ty == IceType_i64) {
       Operand *Lo = loOperand(Arg);
       Operand *Hi = hiOperand(Arg);
-      GPRArgs.push_back(
-          std::make_pair(Lo, RegARM32::getI64PairFirstGPRNum(Reg)));
-      GPRArgs.push_back(
-          std::make_pair(Hi, RegARM32::getI64PairSecondGPRNum(Reg)));
+      GPRArgs.push_back(std::make_pair(
+          Lo, RegNumT::fixme(RegARM32::getI64PairFirstGPRNum(Reg))));
+      GPRArgs.push_back(std::make_pair(
+          Hi, RegNumT::fixme(RegARM32::getI64PairSecondGPRNum(Reg))));
     } else if (isScalarIntegerType(Ty)) {
       GPRArgs.push_back(std::make_pair(Arg, Reg));
     } else {
       FPArgs.push_back(std::make_pair(Arg, Reg));
     }
   }
 
   // Adjust the parameter area so that the stack is aligned. It is assumed that
   // the stack is already aligned at the start of the calling sequence.
   ParameterAreaSizeBytes = applyStackAlignment(ParameterAreaSizeBytes);
@@ skipping 2081 matching lines @@
 }
 
 void TargetARM32::lowerUnreachable(const InstUnreachable * /*Instr*/) {
   _trap();
 }
 
 void TargetARM32::prelowerPhis() {
   PhiLowering::prelowerPhis32Bit<TargetARM32>(this, Context.getNode(), Func);
 }
 
-Variable *TargetARM32::makeVectorOfZeros(Type Ty, int32_t RegNum) {
+Variable *TargetARM32::makeVectorOfZeros(Type Ty, RegNumT RegNum) {
   Variable *Reg = makeReg(Ty, RegNum);
   Context.insert<InstFakeDef>(Reg);
   assert(isVectorType(Ty));
   _veor(Reg, Reg, Reg);
   return Reg;
 }
 
 // Helper for legalize() to emit the right code to lower an operand to a
 // register of the appropriate type.
-Variable *TargetARM32::copyToReg(Operand *Src, int32_t RegNum) {
+Variable *TargetARM32::copyToReg(Operand *Src, RegNumT RegNum) {
   Type Ty = Src->getType();
   Variable *Reg = makeReg(Ty, RegNum);
   if (auto *Mem = llvm::dyn_cast<OperandARM32Mem>(Src)) {
     _ldr(Reg, Mem);
   } else {
     _mov(Reg, Src);
   }
   return Reg;
 }
 
 // TODO(jpp): remove unneeded else clauses in legalize.
 Operand *TargetARM32::legalize(Operand *From, LegalMask Allowed,
-                               int32_t RegNum) {
+                               RegNumT RegNum) {
   Type Ty = From->getType();
   // Assert that a physical register is allowed. To date, all calls to
   // legalize() allow a physical register. Legal_Flex converts registers to the
   // right type OperandARM32FlexReg as needed.
   assert(Allowed & Legal_Reg);
 
   // Copied ipsis literis from TargetX86Base<Machine>.
-  if (RegNum == Variable::NoRegister) {
+  if (RegNum == RegNumT::NoRegister) {
     if (Variable *Subst = getContext().availabilityGet(From)) {
       // At this point we know there is a potential substitution available.
       if (!Subst->isRematerializable() && Subst->mustHaveReg() &&
           !Subst->hasReg()) {
         // At this point we know the substitution will have a register.
         if (From->getType() == Subst->getType()) {
           // At this point we know the substitution's register is compatible.
           return Subst;
         }
       }
@@ skipping 163 matching lines @@
     }
     // Check if the variable is guaranteed a physical register. This can happen
     // either when the variable is pre-colored or when it is assigned infinite
     // weight.
     bool MustHaveRegister = (Var->hasReg() || Var->mustHaveReg());
     // We need a new physical register for the operand if:
     //   Mem is not allowed and Var isn't guaranteed a physical
     //   register, or
     //   RegNum is required and Var->getRegNum() doesn't match.
     if ((!(Allowed & Legal_Mem) && !MustHaveRegister) ||
-        (RegNum != Variable::NoRegister && RegNum != Var->getRegNum())) {
+        (RegNum != RegNumT::NoRegister && RegNum != Var->getRegNum())) {
       From = copyToReg(From, RegNum);
     }
     return From;
   }
   llvm::report_fatal_error("Unhandled operand kind in legalize()");
 
   return From;
 }
 
 /// Provide a trivial wrapper to legalize() for this common usage.
-Variable *TargetARM32::legalizeToReg(Operand *From, int32_t RegNum) {
+Variable *TargetARM32::legalizeToReg(Operand *From, RegNumT RegNum) {
   return llvm::cast<Variable>(legalize(From, Legal_Reg, RegNum));
 }
 
 /// Legalize undef values to concrete values.
-Operand *TargetARM32::legalizeUndef(Operand *From, int32_t RegNum) {
+Operand *TargetARM32::legalizeUndef(Operand *From, RegNumT RegNum) {
   Type Ty = From->getType();
   if (llvm::isa<ConstantUndef>(From)) {
     // Lower undefs to zero. Another option is to lower undefs to an
     // uninitialized register; however, using an uninitialized register results
     // in less predictable code.
     //
     // If in the future the implementation is changed to lower undef values to
     // uninitialized registers, a FakeDef will be needed:
     // Context.insert(InstFakeDef::create(Func, Reg)); This is in order to
     // ensure that the live range of Reg is not overestimated. If the constant
@@ skipping 27 matching lines @@
 Variable64On32 *TargetARM32::makeI64RegPair() {
   Variable64On32 *Reg =
       llvm::cast<Variable64On32>(Func->makeVariable(IceType_i64));
   Reg->setMustHaveReg();
   Reg->initHiLo(Func);
   Reg->getLo()->setMustNotHaveReg();
   Reg->getHi()->setMustNotHaveReg();
   return Reg;
 }
 
-Variable *TargetARM32::makeReg(Type Type, int32_t RegNum) {
+Variable *TargetARM32::makeReg(Type Type, RegNumT RegNum) {
   // There aren't any 64-bit integer registers for ARM32.
   assert(Type != IceType_i64);
-  assert(AllowTemporaryWithNoReg || RegNum != Variable::NoRegister);
+  assert(AllowTemporaryWithNoReg || RegNum != RegNumT::NoRegister);
   Variable *Reg = Func->makeVariable(Type);
-  if (RegNum == Variable::NoRegister)
+  if (RegNum == RegNumT::NoRegister)
     Reg->setMustHaveReg();
   else
     Reg->setRegNum(RegNum);
   return Reg;
 }
 
 void TargetARM32::alignRegisterPow2(Variable *Reg, uint32_t Align,
-                                    int32_t TmpRegNum) {
+                                    RegNumT TmpRegNum) {
   assert(llvm::isPowerOf2_32(Align));
   uint32_t RotateAmt;
   uint32_t Immed_8;
   Operand *Mask;
   // Use AND or BIC to mask off the bits, depending on which immediate fits (if
   // it fits at all). Assume Align is usually small, in which case BIC works
   // better. Thus, this rounds down to the alignment.
   if (OperandARM32FlexImm::canHoldImm(Align - 1, &RotateAmt, &Immed_8)) {
     Mask = legalize(Ctx->getConstantInt32(Align - 1), Legal_Reg | Legal_Flex,
                     TmpRegNum);
     _bic(Reg, Reg, Mask);
   } else {
     Mask = legalize(Ctx->getConstantInt32(-Align), Legal_Reg | Legal_Flex,
                     TmpRegNum);
     _and(Reg, Reg, Mask);
   }
 }
 
 void TargetARM32::postLower() {
   if (Ctx->getFlags().getOptLevel() == Opt_m1)
     return;
   markRedefinitions();
   Context.availabilityUpdate();
 }
 
 void TargetARM32::makeRandomRegisterPermutation(
-    llvm::SmallVectorImpl<int32_t> &Permutation,
+    llvm::SmallVectorImpl<RegNumT> &Permutation,
     const llvm::SmallBitVector &ExcludeRegisters, uint64_t Salt) const {
   (void)Permutation;
   (void)ExcludeRegisters;
   (void)Salt;
   UnimplementedError(Func->getContext()->getFlags());
 }
 
 void TargetARM32::emit(const ConstantInteger32 *C) const {
   if (!BuildDefs::dump())
     return;
@@ skipping 734 matching lines @@
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM];
 llvm::SmallBitVector
     TargetARM32::TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM];
 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 
 } // end of namespace ARM32
 } // end of namespace Ice