Subzero: Use a proper RegNumT type instead of int32_t/SizeT.

src/IceInstX86BaseImpl.h

 //===- subzero/src/IceInstX86BaseImpl.h - Generic X86 instructions -*- C++ -*=//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 870 matching lines @@
     (Asm->*(Emitter.XmmAddr))(Ty, VarReg, Mem->toAsmAddress(Asm, Target));
   } else if (const auto *Imm = llvm::dyn_cast<Constant>(Src)) {
     (Asm->*(Emitter.XmmAddr))(Ty, VarReg,
                               Traits::Address::ofConstPool(Asm, Imm));
   } else {
     llvm_unreachable("Unexpected operand type");
   }
 }
 
 template <typename TraitsType>
-template <typename DReg_t, typename SReg_t, DReg_t (*destEnc)(int32_t),
-          SReg_t (*srcEnc)(int32_t)>
+template <typename DReg_t, typename SReg_t, DReg_t (*destEnc)(RegNumT),
+          SReg_t (*srcEnc)(RegNumT)>
 void InstImpl<TraitsType>::emitIASCastRegOp(
     const Cfg *Func, Type DestTy, const Variable *Dest, Type SrcTy,
     const Operand *Src, const CastEmitterRegOp<DReg_t, SReg_t> &Emitter) {
   auto *Target = InstX86Base::getTarget(Func);
   Assembler *Asm = Func->getAssembler<Assembler>();
   assert(Dest->hasReg());
   DReg_t DestReg = destEnc(Dest->getRegNum());
   if (const auto *SrcVar = llvm::dyn_cast<Variable>(Src)) {
     if (SrcVar->hasReg()) {
       SReg_t SrcReg = srcEnc(SrcVar->getRegNum());
       (Asm->*(Emitter.RegReg))(DestTy, DestReg, SrcTy, SrcReg);
     } else {
       Address SrcStackAddr = Target->stackVarToAsmOperand(SrcVar);
       (Asm->*(Emitter.RegAddr))(DestTy, DestReg, SrcTy, SrcStackAddr);
     }
   } else if (const auto *Mem = llvm::dyn_cast<X86OperandMem>(Src)) {
     Mem->emitSegmentOverride(Asm);
     (Asm->*(Emitter.RegAddr))(DestTy, DestReg, SrcTy,
                               Mem->toAsmAddress(Asm, Target));
   } else {
     llvm_unreachable("Unexpected operand type");
   }
 }
 
 template <typename TraitsType>
-template <typename DReg_t, typename SReg_t, DReg_t (*destEnc)(int32_t),
-          SReg_t (*srcEnc)(int32_t)>
+template <typename DReg_t, typename SReg_t, DReg_t (*destEnc)(RegNumT),
+          SReg_t (*srcEnc)(RegNumT)>
 void InstImpl<TraitsType>::emitIASThreeOpImmOps(
     const Cfg *Func, Type DispatchTy, const Variable *Dest, const Operand *Src0,
     const Operand *Src1, const ThreeOpImmEmitter<DReg_t, SReg_t> Emitter) {
   auto *Target = InstX86Base::getTarget(Func);
   Assembler *Asm = Func->getAssembler<Assembler>();
   // This only handles Dest being a register, and Src1 being an immediate.
   assert(Dest->hasReg());
   DReg_t DestReg = destEnc(Dest->getRegNum());
   AssemblerImmediate Imm(llvm::cast<ConstantInteger32>(Src1)->getValue());
   if (const auto *SrcVar = llvm::dyn_cast<Variable>(Src0)) {
@@ skipping 254 matching lines @@
                                               this->getSrc(2), Emitter);
 }
 
 template <typename TraitsType>
 void InstImpl<TraitsType>::InstX86Cbwdq::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(this->getSrcSize() == 1);
   Operand *Src0 = this->getSrc(0);
-  int32_t DestReg = this->getDest()->getRegNum();
-  int32_t SrcReg = llvm::cast<Variable>(Src0)->getRegNum();
+  const auto DestReg = this->getDest()->getRegNum();
+  const auto SrcReg = llvm::cast<Variable>(Src0)->getRegNum();
   (void)DestReg;
   (void)SrcReg;
   switch (Src0->getType()) {
   default:
     llvm_unreachable("unexpected source type!");
     break;
   case IceType_i8:
     assert(SrcReg == RegisterSet::Reg_al);
     assert(DestReg == RegisterSet::Reg_ax || DestReg == RegisterSet::Reg_ah);
     Str << "\t"
@@ skipping 19 matching lines @@
            "cqo";
     break;
   }
 }
 
 template <typename TraitsType>
 void InstImpl<TraitsType>::InstX86Cbwdq::emitIAS(const Cfg *Func) const {
   Assembler *Asm = Func->getAssembler<Assembler>();
   assert(this->getSrcSize() == 1);
   Operand *Src0 = this->getSrc(0);
-  int32_t DestReg = this->getDest()->getRegNum();
-  int32_t SrcReg = llvm::cast<Variable>(Src0)->getRegNum();
+  const auto DestReg = this->getDest()->getRegNum();
+  const auto SrcReg = llvm::cast<Variable>(Src0)->getRegNum();
   (void)DestReg;
   (void)SrcReg;
   switch (Src0->getType()) {
   default:
     llvm_unreachable("unexpected source type!");
     break;
   case IceType_i8:
     assert(SrcReg == RegisterSet::Reg_al);
     assert(DestReg == RegisterSet::Reg_ax || DestReg == RegisterSet::Reg_ah);
     Asm->cbw();
@@ skipping 733 matching lines @@
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(this->getSrcSize() == 1);
   assert(this->getDest()->hasReg());
   Str << "\t"
          "lea" << this->getWidthString(this->getDest()->getType()) << "\t";
   Operand *Src0 = this->getSrc(0);
   if (const auto *Src0Var = llvm::dyn_cast<Variable>(Src0)) {
     Type Ty = Src0Var->getType();
     // lea on x86-32 doesn't accept mem128 operands, so cast VSrc0 to an
     // acceptable type.
-    Src0Var->asType(isVectorType(Ty) ? IceType_i32 : Ty, Variable::NoRegister)
+    Src0Var->asType(isVectorType(Ty) ? IceType_i32 : Ty, RegNumT::NoRegister)
         ->emit(Func);
   } else {
     Src0->emit(Func);
   }
   Str << ", ";
   this->getDest()->emit(Func);
 }
 
 template <typename TraitsType>
 void InstImpl<TraitsType>::InstX86Mov::emit(const Cfg *Func) const {
@@ skipping 17 matching lines @@
   }
   // For an integer truncation operation, src is wider than dest. In this case,
   // we use a mov instruction whose data width matches the narrower dest.
   // TODO: This assert disallows usages such as copying a floating
   // point value between a vector and a scalar (which movss is used for). Clean
   // this up.
   assert(InstX86Base::getTarget(Func)->typeWidthInBytesOnStack(DestTy) ==
          InstX86Base::getTarget(Func)->typeWidthInBytesOnStack(SrcTy));
   const Operand *NewSrc = Src;
   if (auto *SrcVar = llvm::dyn_cast<Variable>(Src)) {
-    int32_t NewRegNum = Variable::NoRegister;
+    auto NewRegNum = RegNumT::NoRegister;
     if (SrcVar->hasReg())
       NewRegNum = Traits::getGprForType(DestTy, SrcVar->getRegNum());
     if (SrcTy != DestTy)
       NewSrc = SrcVar->asType(DestTy, NewRegNum);
   }
   NewSrc->emit(Func);
   Str << ", ";
   this->getDest()->emit(Func);
 }
 
@@ skipping 505 matching lines @@
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(this->getSrcSize() == 3);
   Str << "\t" << this->Opcode
       << Traits::TypeAttributes[this->getDest()->getType()].PackString << "\t";
   this->getSrc(2)->emit(Func);
   Str << ", ";
   Operand *Src1 = this->getSrc(1);
   if (const auto *Src1Var = llvm::dyn_cast<Variable>(Src1)) {
     // If src1 is a register, it should always be r32.
     if (Src1Var->hasReg()) {
-      int32_t NewRegNum = Traits::getBaseReg(Src1Var->getRegNum());
+      const auto NewRegNum = Traits::getBaseReg(Src1Var->getRegNum());
       const Variable *NewSrc = Src1Var->asType(IceType_i32, NewRegNum);
       NewSrc->emit(Func);
     } else {
       Src1Var->emit(Func);
     }
   } else {
     Src1->emit(Func);
   }
   Str << ", ";
   this->getDest()->emit(Func);
 }
 
 template <typename TraitsType>
 void InstImpl<TraitsType>::InstX86Pinsr::emitIAS(const Cfg *Func) const {
   assert(this->getSrcSize() == 3);
   assert(this->getDest() == this->getSrc(0));
   // pinsrb and pinsrd are SSE4.1 instructions.
   const Operand *Src0 = this->getSrc(1);
   Type DispatchTy = Src0->getType();
   // If src1 is a register, it should always be r32 (this should fall out from
   // the encodings for ByteRegs overlapping the encodings for r32), but we have
   // to make sure the register allocator didn't choose an 8-bit high register
   // like "ah".
   if (BuildDefs::asserts()) {
     if (auto *Src0Var = llvm::dyn_cast<Variable>(Src0)) {
       if (Src0Var->hasReg()) {
-        int32_t RegNum = Src0Var->getRegNum();
-        int32_t BaseRegNum = Traits::getBaseReg(RegNum);
+        const auto RegNum = Src0Var->getRegNum();
+        const auto BaseRegNum = Traits::getBaseReg(RegNum);
         (void)BaseRegNum;
         assert(Traits::getEncodedGPR(RegNum) ==
                Traits::getEncodedGPR(BaseRegNum));
       }
     }
   }
   static const ThreeOpImmEmitter<XmmRegister, GPRRegister> Emitter = {
       &Assembler::pinsr, &Assembler::pinsr};
   emitIASThreeOpImmOps<XmmRegister, GPRRegister, Traits::getEncodedXmm,
                        Traits::getEncodedGPR>(Func, DispatchTy, this->getDest(),
@@ skipping 296 matching lines @@
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "IACA_END";
 }
 
 } // end of namespace X86NAMESPACE
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEINSTX86BASEIMPL_H