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Side by Side Diff: src/IceInstX86Base.h

Issue 1676123002: Subzero: Use a proper RegNumT type instead of int32_t/SizeT. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Make it possible to do "auto NewReg = RegNumT::NoRegister;" Created 4 years, 10 months ago
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1 //===- subzero/src/IceInstX86Base.h - Generic x86 instructions -*- C++ -*--===// 1 //===- subzero/src/IceInstX86Base.h - Generic x86 instructions -*- C++ -*--===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 /// 9 ///
10 /// \file 10 /// \file
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492 492
493 static void emitIASRegOpTyXMM(const Cfg *Func, Type Ty, const Variable *Var, 493 static void emitIASRegOpTyXMM(const Cfg *Func, Type Ty, const Variable *Var,
494 const Operand *Src, 494 const Operand *Src,
495 const XmmEmitterRegOp &Emitter); 495 const XmmEmitterRegOp &Emitter);
496 496
497 static void emitIASGPRShiftDouble(const Cfg *Func, const Variable *Dest, 497 static void emitIASGPRShiftDouble(const Cfg *Func, const Variable *Dest,
498 const Operand *Src1Op, 498 const Operand *Src1Op,
499 const Operand *Src2Op, 499 const Operand *Src2Op,
500 const GPREmitterShiftD &Emitter); 500 const GPREmitterShiftD &Emitter);
501 501
502 template <typename DReg_t, typename SReg_t, DReg_t (*destEnc)(int32_t), 502 template <typename DReg_t, typename SReg_t, DReg_t (*destEnc)(RegNumT),
503 SReg_t (*srcEnc)(int32_t)> 503 SReg_t (*srcEnc)(RegNumT)>
504 static void emitIASCastRegOp(const Cfg *Func, Type DestTy, 504 static void emitIASCastRegOp(const Cfg *Func, Type DestTy,
505 const Variable *Dest, Type SrcTy, 505 const Variable *Dest, Type SrcTy,
506 const Operand *Src, 506 const Operand *Src,
507 const CastEmitterRegOp<DReg_t, SReg_t> &Emitter); 507 const CastEmitterRegOp<DReg_t, SReg_t> &Emitter);
508 508
509 template <typename DReg_t, typename SReg_t, DReg_t (*destEnc)(int32_t), 509 template <typename DReg_t, typename SReg_t, DReg_t (*destEnc)(RegNumT),
510 SReg_t (*srcEnc)(int32_t)> 510 SReg_t (*srcEnc)(RegNumT)>
511 static void 511 static void
512 emitIASThreeOpImmOps(const Cfg *Func, Type DispatchTy, const Variable *Dest, 512 emitIASThreeOpImmOps(const Cfg *Func, Type DispatchTy, const Variable *Dest,
513 const Operand *Src0, const Operand *Src1, 513 const Operand *Src0, const Operand *Src1,
514 const ThreeOpImmEmitter<DReg_t, SReg_t> Emitter); 514 const ThreeOpImmEmitter<DReg_t, SReg_t> Emitter);
515 515
516 static void emitIASMovlikeXMM(const Cfg *Func, const Variable *Dest, 516 static void emitIASMovlikeXMM(const Cfg *Func, const Variable *Dest,
517 const Operand *Src, 517 const Operand *Src,
518 const XmmEmitterMovOps Emitter); 518 const XmmEmitterMovOps Emitter);
519 519
520 static void emitVariableBlendInst(const char *Opcode, const Inst *Instr, 520 static void emitVariableBlendInst(const char *Opcode, const Inst *Instr,
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1038 if (const auto *SrcVar = 1038 if (const auto *SrcVar =
1039 llvm::dyn_cast<const Variable>(this->getSrc(0))) { 1039 llvm::dyn_cast<const Variable>(this->getSrc(0))) {
1040 if (SrcVar->hasReg() && this->Dest->hasReg()) { 1040 if (SrcVar->hasReg() && this->Dest->hasReg()) {
1041 // An assignment between physical registers is considered redundant if 1041 // An assignment between physical registers is considered redundant if
1042 // they have the same base register and the same encoding. E.g.: 1042 // they have the same base register and the same encoding. E.g.:
1043 // mov cl, ecx ==> redundant 1043 // mov cl, ecx ==> redundant
1044 // mov ch, ecx ==> not redundant due to different encodings 1044 // mov ch, ecx ==> not redundant due to different encodings
1045 // mov ch, ebp ==> not redundant due to different base registers 1045 // mov ch, ebp ==> not redundant due to different base registers
1046 // mov ecx, ecx ==> redundant, and dangerous in x86-64. i64 zexting 1046 // mov ecx, ecx ==> redundant, and dangerous in x86-64. i64 zexting
1047 // is handled by Inst86Zext. 1047 // is handled by Inst86Zext.
1048 const int32_t SrcReg = SrcVar->getRegNum(); 1048 const auto SrcReg = SrcVar->getRegNum();
1049 const int32_t DestReg = this->Dest->getRegNum(); 1049 const auto DestReg = this->Dest->getRegNum();
1050 return (Traits::getEncoding(SrcReg) == 1050 return (Traits::getEncoding(SrcReg) ==
1051 Traits::getEncoding(DestReg)) && 1051 Traits::getEncoding(DestReg)) &&
1052 (Traits::getBaseReg(SrcReg) == Traits::getBaseReg(DestReg)); 1052 (Traits::getBaseReg(SrcReg) == Traits::getBaseReg(DestReg));
1053 } 1053 }
1054 } 1054 }
1055 return checkForRedundantAssign(this->getDest(), this->getSrc(0)); 1055 return checkForRedundantAssign(this->getDest(), this->getSrc(0));
1056 } 1056 }
1057 bool isVarAssign() const override { 1057 bool isVarAssign() const override {
1058 return llvm::isa<Variable>(this->getSrc(0)); 1058 return llvm::isa<Variable>(this->getSrc(0));
1059 } 1059 }
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3528 &InstImpl<TraitsType>::Assembler::psrl}; \ 3528 &InstImpl<TraitsType>::Assembler::psrl}; \
3529 } \ 3529 } \
3530 } 3530 }
3531 3531
3532 } // end of namespace X86NAMESPACE 3532 } // end of namespace X86NAMESPACE
3533 } // end of namespace Ice 3533 } // end of namespace Ice
3534 3534
3535 #include "IceInstX86BaseImpl.h" 3535 #include "IceInstX86BaseImpl.h"
3536 3536
3537 #endif // SUBZERO_SRC_ICEINSTX86BASE_H 3537 #endif // SUBZERO_SRC_ICEINSTX86BASE_H
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