Subzero: Use a proper RegNumT type instead of int32_t/SizeT.

src/IceInstARM32.cpp

 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 870 matching lines @@
 }
 
 void InstARM32RegisterStackOp::emitSRegsAsText(const Cfg *Func,
                                                const Variable *BaseReg,
                                                SizeT RegCount) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   Str << "\t" << getSRegOpcode() << "\t{";
   bool IsFirst = true;
-  int32_t Base = BaseReg->getRegNum();
+  const auto Base = BaseReg->getRegNum();
   for (SizeT i = 0; i < RegCount; ++i) {
     if (IsFirst)
       IsFirst = false;
     else
       Str << ", ";
-    Str << RegARM32::getRegName(Base + i);
+    Str << RegARM32::getRegName(RegNumT::fixme(Base + i));
   }
   Str << "}";
 }
 
 void InstARM32RegisterStackOp::emitSRegsOp(const Cfg *Func, EmitForm Form,
                                            const Variable *BaseReg,
                                            SizeT RegCount,
                                            SizeT InstIndex) const {
   if (Form == Emit_Text && BuildDefs::dump() && InstIndex > 0) {
     startNextInst(Func);
     Func->getContext()->getStrEmit() << "\n";
   }
   emitSRegs(Func, Form, BaseReg, RegCount);
 }
 
 namespace {
 
 bool isAssignedConsecutiveRegisters(const Variable *Before,
                                     const Variable *After) {
-  return RegARM32::getEncodedSReg(Before->getRegNum()) + 1 ==
-         RegARM32::getEncodedSReg(After->getRegNum());
+  assert(Before->hasReg());
+  assert(After->hasReg());
+  return RegNumT::fixme(Before->getRegNum() + 1) == After->getRegNum();
 }
 
 } // end of anonymous namespace
 
 void InstARM32RegisterStackOp::emitUsingForm(const Cfg *Func,
                                              const EmitForm Form) const {
   SizeT NumRegs = getNumStackRegs();
   assert(NumRegs);
 
   const auto *Reg = llvm::cast<Variable>(getStackReg(0));
   if (isScalarIntegerType(Reg->getType())) {
     // Push/pop GPR registers.
     SizeT IntegerCount = 0;
     ARM32::IValueT GPRegisters = 0;
     const Variable *LastDest = nullptr;
     for (SizeT i = 0; i < NumRegs; ++i) {
       const Variable *Var = getStackReg(i);
       assert(Var->hasReg() && "stack op only applies to registers");
-      int32_t Reg = RegARM32::getEncodedGPR(Var->getRegNum());
+      const RegARM32::GPRRegister Reg =
+          RegARM32::getEncodedGPR(Var->getRegNum());
       LastDest = Var;
       GPRegisters |= (1 << Reg);
       ++IntegerCount;
     }
     if (IntegerCount == 1) {
       emitSingleGPR(Func, Form, LastDest);
     } else {
       emitMultipleGPRs(Func, Form, GPRegisters);
     }
     return;
@@ skipping 114 matching lines @@
   } else {
     addSource(Src64->getLo());
     addSource(Src64->getHi());
   }
 }
 
 // These next two functions find the D register that maps to the half of the Q
 // register that this instruction is accessing.
 Register getDRegister(const Variable *Src, uint32_t Index) {
   assert(Src->hasReg());
-  const auto SrcReg = static_cast<Register>(Src->getRegNum());
+  const auto SrcReg = Src->getRegNum();
 
   const RegARM32::RegTableType &SrcEntry = RegARM32::RegTable[SrcReg];
   assert(SrcEntry.IsVec128);
 
   const uint32_t NumElements = typeNumElements(Src->getType());
 
   // This code assumes the Aliases list goes Q_n, S_2n, S_2n+1. The asserts in
   // the next two branches help to check that this is still true.
   if (Index < NumElements / 2) {
     // We have a Q register that's made up of two D registers. This assert is
@@ skipping 17 matching lines @@
 }
 
 constexpr uint32_t getDIndex(uint32_t NumElements, uint32_t Index) {
   return (Index < NumElements / 2) ? Index : Index - (NumElements / 2);
 }
 
 // For floating point values, we can insertelement or extractelement by moving
 // directly from an S register. This function finds the right one.
 Register getSRegister(const Variable *Src, uint32_t Index) {
   assert(Src->hasReg());
-  const auto SrcReg = static_cast<Register>(Src->getRegNum());
+  const auto SrcReg = Src->getRegNum();
 
   // For floating point values, we need to be allocated to Q0 - Q7, so we can
   // directly access the value we want as one of the S registers.
   assert(Src->getType() == IceType_v4f32);
   assert(SrcReg < RegARM32::Reg_q8);
 
   // This part assumes the register alias list goes q0, d0, d1, s0, s1, s2, s3.
   assert(Index < 4);
 
   // TODO(jpp): find a way to do this that doesn't rely on ordering of the alias
@@ skipping 1591 matching lines @@
 
 template class InstARM32FourAddrGPR<InstARM32::Mla>;
 template class InstARM32FourAddrGPR<InstARM32::Mls>;
 
 template class InstARM32CmpLike<InstARM32::Cmn>;
 template class InstARM32CmpLike<InstARM32::Cmp>;
 template class InstARM32CmpLike<InstARM32::Tst>;
 
 } // end of namespace ARM32
 } // end of namespace Ice