Subzero: Use a proper RegNumT type instead of int32_t/SizeT.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 177 matching lines @@
 // Extract out a Bit in Value.
 bool isBitSet(IValueT Bit, IValueT Value) { return (Value & Bit) == Bit; }
 
 // Returns the GPR register at given Shift in Value.
 RegARM32::GPRRegister getGPRReg(IValueT Shift, IValueT Value) {
   return decodeGPRRegister((Value >> Shift) & 0xF);
 }
 
 IValueT getEncodedGPRegNum(const Variable *Var) {
   assert(Var->hasReg());
-  int32_t Reg = Var->getRegNum();
+  const auto Reg = Var->getRegNum();
   return llvm::isa<Variable64On32>(Var) ? RegARM32::getI64PairFirstGPRNum(Reg)
                                         : RegARM32::getEncodedGPR(Reg);
 }
 
 IValueT getEncodedSRegNum(const Variable *Var) {
   assert(Var->hasReg());
   return RegARM32::getEncodedSReg(Var->getRegNum());
 }
 
 IValueT getEncodedDRegNum(const Variable *Var) {
@@ skipping 254 matching lines @@
                              const AssemblerARM32::TargetInfo &TInfo,
                              EncodedImmAddress ImmEncoding) {
   Value = 0; // Make sure initialized.
   if (const auto *Var = llvm::dyn_cast<Variable>(Opnd)) {
     // Should be a stack variable, with an offset.
     if (Var->hasReg())
       return CantEncode;
     IOffsetT Offset = Var->getStackOffset();
     if (!Utils::IsAbsoluteUint(12, Offset))
       return CantEncode;
-    int32_t BaseRegNum = Var->getBaseRegNum();
-    if (BaseRegNum == Variable::NoRegister)
-      BaseRegNum = TInfo.FrameOrStackReg;
+    const auto BaseRegNum =
+        Var->hasReg() ? Var->getBaseRegNum() : TInfo.FrameOrStackReg;
     Value = encodeImmRegOffset(ImmEncoding, BaseRegNum, Offset,
                                OperandARM32Mem::Offset);
     return EncodedAsImmRegOffset;
   }
   if (const auto *Mem = llvm::dyn_cast<OperandARM32Mem>(Opnd)) {
     Variable *Var = Mem->getBase();
     if (!Var->hasReg())
       return CantEncode;
     IValueT Rn = getEncodedGPRegNum(Var);
     if (Mem->isRegReg()) {
@@ skipping 92 matching lines @@
     llvm::report_fatal_error(std::string(InstName) + ": " + RegName +
                              "=pc not allowed");
 }
 
 void verifyRegNotPcWhenSetFlags(IValueT Reg, bool SetFlags,
                                 const char *InstName) {
   if (BuildDefs::minimal())
     return;
   if (SetFlags && (Reg == RegARM32::Encoded_Reg_pc))
     llvm::report_fatal_error(std::string(InstName) + ": " +
-                             RegARM32::getRegName(Reg) +
+                             RegARM32::getRegName(RegARM32::Reg_pc) +
                              "=pc not allowed when CC=1");
 }
 
 } // end of anonymous namespace
 
 namespace Ice {
 namespace ARM32 {
 
 size_t MoveRelocatableFixup::emit(GlobalContext *Ctx,
                                   const Assembler &Asm) const {
   if (!BuildDefs::dump())
     return InstARM32::InstSize;
   Ostream &Str = Ctx->getStrEmit();
   IValueT Inst = Asm.load<IValueT>(position());
   Str << "\t"
          "mov" << (kind() == llvm::ELF::R_ARM_MOVW_ABS_NC ? "w" : "t") << "\t"
-      << RegARM32::getRegName((Inst >> kRdShift) & 0xF)
+      << RegARM32::getRegName(RegNumT::fixme((Inst >> kRdShift) & 0xF))
       << ", #:" << (kind() == llvm::ELF::R_ARM_MOVW_ABS_NC ? "lower" : "upper")
       << "16:" << symbol(Ctx, &Asm) << "\t@ .word "
       << llvm::format_hex_no_prefix(Inst, 8) << "\n";
   return InstARM32::InstSize;
 }
 
 // This fixup points to an ARM32 instruction with the following format:
 void MoveRelocatableFixup::emitOffset(Assembler *Asm) const {
   // cccc00110T00iiiiddddiiiiiiiiiiii where cccc=Cond, dddd=Rd,
   // iiiiiiiiiiiiiiii = Imm16, and T=1 for movt.
@@ skipping 2435 matching lines @@
   constexpr const char *Vsqrts = "vsqrts";
   IValueT Sd = encodeSRegister(OpSd, "Sd", Vsqrts);
   IValueT Sm = encodeSRegister(OpSm, "Sm", Vsqrts);
   constexpr IValueT VsqrtsOpcode = B23 | B21 | B20 | B16 | B7 | B6;
   constexpr IValueT S0 = 0;
   emitVFPsss(Cond, VsqrtsOpcode, Sd, S0, Sm);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice