Subzero: Use a proper RegNumT type instead of int32_t/SizeT.

src/IceTargetLoweringX86BaseImpl.h

 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 359 matching lines @@
       TargetInstructionSet::BaseInstructionSet) {
     InstructionSet = static_cast<InstructionSetEnum>(
         (Func->getContext()->getFlags().getTargetInstructionSet() -
          TargetInstructionSet::X86InstructionSet_Begin) +
         Traits::InstructionSet::Begin);
   }
 }
 
 template <typename TraitsType>
 void TargetX86Base<TraitsType>::staticInit(GlobalContext *Ctx) {
+  RegNumT::setLimit(Traits::RegisterSet::Reg_NUM);
   Traits::initRegisterSet(Ctx->getFlags(), &TypeToRegisterSet,
                           &RegisterAliases);
   for (size_t i = 0; i < TypeToRegisterSet.size(); ++i)
     TypeToRegisterSetUnfiltered[i] = TypeToRegisterSet[i];
   filterTypeToRegisterSet(Ctx, Traits::RegisterSet::Reg_NUM,
                           TypeToRegisterSet.data(), TypeToRegisterSet.size(),
                           Traits::getRegName, getRegClassName);
   PcRelFixup = Traits::FK_PcRel;
   AbsFixup =
       Ctx->getFlags().getUseNonsfi() ? Traits::FK_Gotoff : Traits::FK_Abs;
@@ skipping 445 matching lines @@
 
 template <typename TraitsType>
 bool TargetX86Base<TraitsType>::doBranchOpt(Inst *I, const CfgNode *NextNode) {
   if (auto *Br = llvm::dyn_cast<InstX86Br>(I)) {
     return Br->optimizeBranch(NextNode);
   }
   return false;
 }
 
 template <typename TraitsType>
-Variable *TargetX86Base<TraitsType>::getPhysicalRegister(SizeT RegNum,
+Variable *TargetX86Base<TraitsType>::getPhysicalRegister(RegNumT RegNum,
                                                          Type Ty) {
   if (Ty == IceType_void)
     Ty = IceType_i32;
   if (PhysicalRegisters[Ty].empty())
     PhysicalRegisters[Ty].resize(Traits::RegisterSet::Reg_NUM);
-  assert(RegNum < PhysicalRegisters[Ty].size());
+  assert(unsigned(RegNum) < PhysicalRegisters[Ty].size());
   Variable *Reg = PhysicalRegisters[Ty][RegNum];
   if (Reg == nullptr) {
     Reg = Func->makeVariable(Ty);
     Reg->setRegNum(RegNum);
     PhysicalRegisters[Ty][RegNum] = Reg;
     // Specially mark a named physical register as an "argument" so that it is
     // considered live upon function entry.  Otherwise it's possible to get
     // liveness validation errors for saving callee-save registers.
     Func->addImplicitArg(Reg);
     // Don't bother tracking the live range of a named physical register.
     Reg->setIgnoreLiveness();
   }
-  assert(Traits::getGprForType(Ty, RegNum) == static_cast<int32_t>(RegNum));
+  assert(Traits::getGprForType(Ty, RegNum) == RegNum);
   return Reg;
 }
 
 template <typename TraitsType>
-IceString TargetX86Base<TraitsType>::getRegName(SizeT RegNum, Type Ty) const {
+IceString TargetX86Base<TraitsType>::getRegName(RegNumT RegNum, Type Ty) const {
   return Traits::getRegName(Traits::getGprForType(Ty, RegNum));
 }
 
 template <typename TraitsType>
 void TargetX86Base<TraitsType>::emitVariable(const Variable *Var) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Ctx->getStrEmit();
   if (Var->hasReg()) {
     const bool Is64BitSandboxing = Traits::Is64Bit && NeedSandboxing;
     const Type VarType = (Var->isRematerializable() && Is64BitSandboxing)
                              ? IceType_i64
                              : Var->getType();
     Str << "%" << getRegName(Var->getRegNum(), VarType);
     return;
   }
   if (Var->mustHaveReg()) {
     llvm::report_fatal_error("Infinite-weight Variable (" + Var->getName(Func) +
                              ") has no register assigned - function " +
                              Func->getFunctionName());
   }
   const int32_t Offset = Var->getStackOffset();
-  int32_t BaseRegNum = Var->getBaseRegNum();
-  if (BaseRegNum == Variable::NoRegister)
+  auto BaseRegNum = Var->getBaseRegNum();
+  if (BaseRegNum == RegNumT::NoRegister)
     BaseRegNum = getFrameOrStackReg();
   // Print in the form "Offset(%reg)", taking care that:
   //   - Offset is never printed when it is 0
 
   const bool DecorateAsm = Func->getContext()->getFlags().getDecorateAsm();
   // Only print Offset when it is nonzero, regardless of DecorateAsm.
   if (Offset) {
     if (DecorateAsm) {
       Str << Var->getSymbolicStackOffset(Func);
     } else {
       Str << Offset;
     }
   }
   const Type FrameSPTy = Traits::WordType;
   Str << "(%" << getRegName(BaseRegNum, FrameSPTy) << ")";
 }
 
 template <typename TraitsType>
 typename TargetX86Base<TraitsType>::X86Address
 TargetX86Base<TraitsType>::stackVarToAsmOperand(const Variable *Var) const {
   if (Var->hasReg())
     llvm::report_fatal_error("Stack Variable has a register assigned");
   if (Var->mustHaveReg()) {
     llvm::report_fatal_error("Infinite-weight Variable (" + Var->getName(Func) +
                              ") has no register assigned - function " +
                              Func->getFunctionName());
   }
   int32_t Offset = Var->getStackOffset();
-  int32_t BaseRegNum = Var->getBaseRegNum();
-  if (Var->getBaseRegNum() == Variable::NoRegister)
+  auto BaseRegNum = Var->getBaseRegNum();
+  if (Var->getBaseRegNum() == RegNumT::NoRegister)
     BaseRegNum = getFrameOrStackReg();
   return X86Address(Traits::getEncodedGPR(BaseRegNum), Offset,
                     AssemblerFixup::NoFixup);
 }
 
 template <typename TraitsType>
 void TargetX86Base<TraitsType>::addProlog(CfgNode *Node) {
   // Stack frame layout:
   //
   // +------------------------+
@@ skipping 73 matching lines @@
   getVarStackSlotParams(SortedSpilledVariables, RegsUsed, &GlobalsSize,
                         &SpillAreaSizeBytes, &SpillAreaAlignmentBytes,
                         &LocalsSlotsAlignmentBytes, TargetVarHook);
   uint32_t LocalsSpillAreaSize = SpillAreaSizeBytes;
   SpillAreaSizeBytes += GlobalsSize;
 
   // Add push instructions for preserved registers.
   uint32_t NumCallee = 0;
   size_t PreservedRegsSizeBytes = 0;
   llvm::SmallBitVector Pushed(CalleeSaves.size());
-  for (SizeT i = 0; i < CalleeSaves.size(); ++i) {
-    const int32_t Canonical = Traits::getBaseReg(i);
+  for (RegNumT i : RegNumBitVector(CalleeSaves)) {
+    const auto Canonical = Traits::getBaseReg(i);
     assert(Canonical == Traits::getBaseReg(Canonical));
-    if (CalleeSaves[i] && RegsUsed[i]) {
+    if (RegsUsed[i]) {
       Pushed[Canonical] = true;
     }
   }
-  for (SizeT i = 0; i < Pushed.size(); ++i) {
-    if (!Pushed[i])
-      continue;
-    assert(static_cast<int32_t>(i) == Traits::getBaseReg(i));
+  for (RegNumT RegNum : RegNumBitVector(Pushed)) {
+    assert(RegNum == Traits::getBaseReg(RegNum));
     ++NumCallee;
     PreservedRegsSizeBytes += typeWidthInBytes(Traits::WordType);
-    _push_reg(getPhysicalRegister(i, Traits::WordType));
+    _push_reg(getPhysicalRegister(RegNum, Traits::WordType));
   }
   Ctx->statsUpdateRegistersSaved(NumCallee);
 
   // Generate "push frameptr; mov frameptr, stackptr"
   if (IsEbpBasedFrame) {
     assert((RegsUsed & getRegisterSet(RegSet_FramePointer, RegSet_None))
                .count() == 0);
     PreservedRegsSizeBytes += typeWidthInBytes(Traits::WordType);
     _link_bp();
   }
@@ skipping 76 matching lines @@
 
   emitGetIP(Node);
 
   const VarList &Args = Func->getArgs();
   size_t InArgsSizeBytes = 0;
   unsigned NumXmmArgs = 0;
   unsigned NumGPRArgs = 0;
   for (Variable *Arg : Args) {
     // Skip arguments passed in registers.
     if (isVectorType(Arg->getType())) {
-      if (Traits::getRegisterForXmmArgNum(NumXmmArgs) != Variable::NoRegister) {
+      if (Traits::getRegisterForXmmArgNum(NumXmmArgs) != RegNumT::NoRegister) {
         ++NumXmmArgs;
         continue;
       }
     } else if (isScalarFloatingType(Arg->getType())) {
       if (Traits::X86_PASS_SCALAR_FP_IN_XMM &&
-          Traits::getRegisterForXmmArgNum(NumXmmArgs) != Variable::NoRegister) {
+          Traits::getRegisterForXmmArgNum(NumXmmArgs) != RegNumT::NoRegister) {
         ++NumXmmArgs;
         continue;
       }
     } else {
       assert(isScalarIntegerType(Arg->getType()));
       if (Traits::getRegisterForGprArgNum(Traits::WordType, NumGPRArgs) !=
-          Variable::NoRegister) {
+          RegNumT::NoRegister) {
         ++NumGPRArgs;
         continue;
       }
     }
     // For esp-based frames where the allocas are done outside the prolog, the
     // esp value may not stabilize to its home value until after all the
     // fixed-size alloca instructions have executed.  In this case, a stack
     // adjustment is needed when accessing in-args in order to copy them into
     // registers.
     size_t StackAdjBytes = 0;
@@ skipping 117 matching lines @@
     if (SpillAreaSizeBytes != 0) {
       _add_sp(Ctx->getConstantInt32(SpillAreaSizeBytes));
     }
   }
 
   // Add pop instructions for preserved registers.
   llvm::SmallBitVector CalleeSaves =
       getRegisterSet(RegSet_CalleeSave, RegSet_None);
   llvm::SmallBitVector Popped(CalleeSaves.size());
   for (int32_t i = CalleeSaves.size() - 1; i >= 0; --i) {
-    if (static_cast<SizeT>(i) == getFrameReg() && IsEbpBasedFrame)
+    auto RegNum = RegNumT::fromInt(i);
+    if (RegNum == getFrameReg() && IsEbpBasedFrame)
       continue;
-    const SizeT Canonical = Traits::getBaseReg(i);
+    const RegNumT Canonical = Traits::getBaseReg(RegNum);
     if (CalleeSaves[i] && RegsUsed[i]) {
       Popped[Canonical] = true;
     }
   }
   for (int32_t i = Popped.size() - 1; i >= 0; --i) {
     if (!Popped[i])
       continue;
-    assert(i == Traits::getBaseReg(i));
-    _pop(getPhysicalRegister(i, Traits::WordType));
+    auto RegNum = RegNumT::fromInt(i);
+    assert(RegNum == Traits::getBaseReg(RegNum));
+    _pop(getPhysicalRegister(RegNum, Traits::WordType));
   }
 
   if (!NeedSandboxing) {
     return;
   }
   emitSandboxedReturn();
   if (RI->getSrcSize()) {
     auto *RetValue = llvm::cast<Variable>(RI->getSrc(0));
     Context.insert<InstFakeUse>(RetValue);
   }
@@ skipping 168 matching lines @@
   bool GprSlotsRemain = true;
 
   Context.init(Func->getEntryNode());
   Context.setInsertPoint(Context.getCur());
 
   for (SizeT i = 0, End = Args.size();
        i < End && (XmmSlotsRemain || GprSlotsRemain); ++i) {
     Variable *Arg = Args[i];
     Type Ty = Arg->getType();
     Variable *RegisterArg = nullptr;
-    int32_t RegNum = Variable::NoRegister;
+    RegNumT RegNum = RegNumT::NoRegister;
     if (isVectorType(Ty)) {
       RegNum = Traits::getRegisterForXmmArgNum(NumXmmArgs);
-      if (RegNum == Variable::NoRegister) {
+      if (RegNum == RegNumT::NoRegister) {
         XmmSlotsRemain = false;
         continue;
       }
       ++NumXmmArgs;
       RegisterArg = Func->makeVariable(Ty);
     } else if (isScalarFloatingType(Ty)) {
       if (!Traits::X86_PASS_SCALAR_FP_IN_XMM) {
         continue;
       }
       RegNum = Traits::getRegisterForXmmArgNum(NumXmmArgs);
-      if (RegNum == Variable::NoRegister) {
+      if (RegNum == RegNumT::NoRegister) {
         XmmSlotsRemain = false;
         continue;
       }
       ++NumXmmArgs;
       RegisterArg = Func->makeVariable(Ty);
     } else if (isScalarIntegerType(Ty)) {
       RegNum = Traits::getRegisterForGprArgNum(Ty, NumGprArgs);
-      if (RegNum == Variable::NoRegister) {
+      if (RegNum == RegNumT::NoRegister) {
         GprSlotsRemain = false;
         continue;
       }
       ++NumGprArgs;
       RegisterArg = Func->makeVariable(Ty);
     }
-    assert(RegNum != Variable::NoRegister);
+    assert(RegNum != RegNumT::NoRegister);
     assert(RegisterArg != nullptr);
     // Replace Arg in the argument list with the home register. Then generate
     // an instruction in the prolog to copy the home register to the assigned
     // location of Arg.
     if (BuildDefs::dump())
       RegisterArg->setName(Func, "home_reg:" + Arg->getName(Func));
     RegisterArg->setRegNum(RegNum);
     RegisterArg->setIsArg();
     Arg->setIsArg(false);
 
@@ skipping 668 matching lines @@
     _mov(T, Src0);
     if (!llvm::isa<ConstantInteger32>(Src1))
       Src1 = copyToReg8(Src1, Traits::RegisterSet::Reg_cl);
     _sar(T, Src1);
     _mov(Dest, T);
     break;
   case InstArithmetic::Udiv: {
     // div and idiv are the few arithmetic operators that do not allow
     // immediates as the operand.
     Src1 = legalize(Src1, Legal_Reg | Legal_Mem);
-    uint32_t Eax;
-    uint32_t Edx;
+    RegNumT Eax;
+    RegNumT Edx;
     switch (Ty) {
     default:
       llvm::report_fatal_error("Bad type for udiv");
     case IceType_i64:
       Eax = Traits::getRaxOrDie();
       Edx = Traits::getRdxOrDie();
       break;
     case IceType_i32:
       Eax = Traits::RegisterSet::Reg_eax;
       Edx = Traits::RegisterSet::Reg_edx;
@@ skipping 68 matching lines @@
       T_edx = makeReg(IceType_i16, Traits::RegisterSet::Reg_ax);
       _mov(T, Src0, Traits::RegisterSet::Reg_al);
       break;
     }
     _cbwdq(T_edx, T);
     _idiv(T, Src1, T_edx);
     _mov(Dest, T);
     break;
   case InstArithmetic::Urem: {
     Src1 = legalize(Src1, Legal_Reg | Legal_Mem);
-    uint32_t Eax;
-    uint32_t Edx;
+    RegNumT Eax;
+    RegNumT Edx;
     switch (Ty) {
     default:
       llvm::report_fatal_error("Bad type for urem");
     case IceType_i64:
       Eax = Traits::getRaxOrDie();
       Edx = Traits::getRdxOrDie();
       break;
     case IceType_i32:
       Eax = Traits::RegisterSet::Reg_eax;
       Edx = Traits::RegisterSet::Reg_edx;
@@ skipping 47 matching lines @@
           _add(T, Src0);
           _and(T, Ctx->getConstantInt(Ty, -(1 << LogDiv)));
           _sub(T, Src0);
           _neg(T);
           _mov(Dest, T);
           return;
         }
       }
     }
     Src1 = legalize(Src1, Legal_Reg | Legal_Mem);
-    uint32_t Eax;
-    uint32_t Edx;
+    RegNumT Eax;
+    RegNumT Edx;
     switch (Ty) {
     default:
       llvm::report_fatal_error("Bad type for srem");
     case IceType_i64:
       Eax = Traits::getRaxOrDie();
       Edx = Traits::getRdxOrDie();
       break;
     case IceType_i32:
       Eax = Traits::RegisterSet::Reg_eax;
       Edx = Traits::RegisterSet::Reg_edx;
@@ skipping 116 matching lines @@
   uint32_t ParameterAreaSizeBytes = 0;
 
   // Classify each argument operand according to the location where the argument
   // is passed.
   for (SizeT i = 0, NumArgs = Instr->getNumArgs(); i < NumArgs; ++i) {
     Operand *Arg = Instr->getArg(i);
     const Type Ty = Arg->getType();
     // The PNaCl ABI requires the width of arguments to be at least 32 bits.
     assert(typeWidthInBytes(Ty) >= 4);
     if (isVectorType(Ty) && (Traits::getRegisterForXmmArgNum(XmmArgs.size()) !=
-                             Variable::NoRegister)) {
+                             RegNumT::NoRegister)) {
       XmmArgs.push_back(Arg);
     } else if (isScalarFloatingType(Ty) && Traits::X86_PASS_SCALAR_FP_IN_XMM &&
                (Traits::getRegisterForXmmArgNum(XmmArgs.size()) !=
-                Variable::NoRegister)) {
+                RegNumT::NoRegister)) {
       XmmArgs.push_back(Arg);
     } else if (isScalarIntegerType(Ty) &&
                (Traits::getRegisterForGprArgNum(Ty, GprArgs.size()) !=
-                Variable::NoRegister)) {
+                RegNumT::NoRegister)) {
       GprArgs.emplace_back(Ty, Arg);
     } else {
       // Place on stack.
       StackArgs.push_back(Arg);
       if (isVectorType(Arg->getType())) {
         ParameterAreaSizeBytes =
             Traits::applyStackAlignment(ParameterAreaSizeBytes);
       }
       Variable *esp = getPhysicalRegister(getStackReg(), Traits::WordType);
       Constant *Loc = Ctx->getConstantInt32(ParameterAreaSizeBytes);
@@ skipping 1755 matching lines @@
     _mov(T_ecx, hiOperand(Desired));
     X86OperandMem *Addr = formMemoryOperand(Ptr, Ty);
     constexpr bool Locked = true;
     _cmpxchg8b(Addr, T_edx, T_eax, T_ecx, T_ebx, Locked);
     auto *DestLo = llvm::cast<Variable>(loOperand(DestPrev));
     auto *DestHi = llvm::cast<Variable>(hiOperand(DestPrev));
     _mov(DestLo, T_eax);
     _mov(DestHi, T_edx);
     return;
   }
-  int32_t Eax;
+  RegNumT Eax;
   switch (Ty) {
   default:
     llvm::report_fatal_error("Bad type for cmpxchg");
   case IceType_i64:
     Eax = Traits::getRaxOrDie();
     break;
   case IceType_i32:
     Eax = Traits::RegisterSet::Reg_eax;
     break;
   case IceType_i16:
@@ skipping 250 matching lines @@
     // The address base (if any) is also reused in the loop.
     if (Variable *Base = Addr->getBase())
       Context.insert<InstFakeUse>(Base);
     auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
     auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
     _mov(DestLo, T_eax);
     _mov(DestHi, T_edx);
     return;
   }
   X86OperandMem *Addr = formMemoryOperand(Ptr, Ty);
-  int32_t Eax;
+  RegNumT Eax;
   switch (Ty) {
   default:
     llvm::report_fatal_error("Bad type for atomicRMW");
   case IceType_i64:
     Eax = Traits::getRaxOrDie();
     break;
   case IceType_i32:
     Eax = Traits::RegisterSet::Reg_eax;
     break;
   case IceType_i16:
@@ skipping 918 matching lines @@
     Opnd = Mem->getBase();
   }
   // At this point Opnd could be nullptr, or Variable, or Constant, or perhaps
   // something else.  We only care if it is Variable.
   auto *Var = llvm::dyn_cast_or_null<Variable>(Opnd);
   if (Var == nullptr)
     return;
   // We use lowerStore() to copy out-args onto the stack.  This creates a memory
   // operand with the stack pointer as the base register.  Don't do bounds
   // checks on that.
-  if (Var->getRegNum() == static_cast<int32_t>(getStackReg()))
+  if (Var->getRegNum() == getStackReg())
     return;
 
   auto *Label = InstX86Label::create(Func, this);
   _cmp(Opnd, Ctx->getConstantZero(IceType_i32));
   _br(Traits::Cond::Br_e, Label);
   _cmp(Opnd, Ctx->getConstantInt32(1));
   _br(Traits::Cond::Br_e, Label);
   Context.insert(Label);
 }
 
@@ skipping 1036 matching lines @@
   // Compute the return type (if any);
   Type ReturnType = IceType_void;
   Variable *Dest = Instr->getDest();
   if (Dest != nullptr)
     ReturnType = Dest->getType();
   return getCallStackArgumentsSizeBytes(ArgTypes, ReturnType);
 }
 
 template <typename TraitsType>
 Variable *TargetX86Base<TraitsType>::makeZeroedRegister(Type Ty,
-                                                        int32_t RegNum) {
+                                                        RegNumT RegNum) {
   Variable *Reg = makeReg(Ty, RegNum);
   switch (Ty) {
   case IceType_i1:
   case IceType_i8:
   case IceType_i16:
   case IceType_i32:
   case IceType_i64:
     // Conservatively do "mov reg, 0" to avoid modifying FLAGS.
     _mov(Reg, Ctx->getConstantZero(Ty));
     break;
@@ skipping 14 matching lines @@
 
 // There is no support for loading or emitting vector constants, so the vector
 // values returned from makeVectorOfZeros, makeVectorOfOnes, etc. are
 // initialized with register operations.
 //
 // TODO(wala): Add limited support for vector constants so that complex
 // initialization in registers is unnecessary.
 
 template <typename TraitsType>
 Variable *TargetX86Base<TraitsType>::makeVectorOfZeros(Type Ty,
-                                                       int32_t RegNum) {
+                                                       RegNumT RegNum) {
   return makeZeroedRegister(Ty, RegNum);
 }
 
 template <typename TraitsType>
 Variable *TargetX86Base<TraitsType>::makeVectorOfMinusOnes(Type Ty,
-                                                           int32_t RegNum) {
+                                                           RegNumT RegNum) {
   Variable *MinusOnes = makeReg(Ty, RegNum);
   // Insert a FakeDef so the live range of MinusOnes is not overestimated.
   Context.insert<InstFakeDef>(MinusOnes);
   if (Ty == IceType_f64)
     // Making a vector of minus ones of type f64 is currently only used for the
     // fabs intrinsic.  To use the f64 type to create this mask with pcmpeqq
     // requires SSE 4.1.  Since we're just creating a mask, pcmpeqd does the
     // same job and only requires SSE2.
     _pcmpeq(MinusOnes, MinusOnes, IceType_f32);
   else
     _pcmpeq(MinusOnes, MinusOnes);
   return MinusOnes;
 }
 
 template <typename TraitsType>
-Variable *TargetX86Base<TraitsType>::makeVectorOfOnes(Type Ty, int32_t RegNum) {
+Variable *TargetX86Base<TraitsType>::makeVectorOfOnes(Type Ty, RegNumT RegNum) {
   Variable *Dest = makeVectorOfZeros(Ty, RegNum);
   Variable *MinusOne = makeVectorOfMinusOnes(Ty);
   _psub(Dest, MinusOne);
   return Dest;
 }
 
 template <typename TraitsType>
 Variable *TargetX86Base<TraitsType>::makeVectorOfHighOrderBits(Type Ty,
-                                                               int32_t RegNum) {
+                                                               RegNumT RegNum) {
   assert(Ty == IceType_v4i32 || Ty == IceType_v4f32 || Ty == IceType_v8i16 ||
          Ty == IceType_v16i8);
   if (Ty == IceType_v4f32 || Ty == IceType_v4i32 || Ty == IceType_v8i16) {
     Variable *Reg = makeVectorOfOnes(Ty, RegNum);
     SizeT Shift =
         typeWidthInBytes(typeElementType(Ty)) * Traits::X86_CHAR_BIT - 1;
     _psll(Reg, Ctx->getConstantInt8(Shift));
     return Reg;
   } else {
     // SSE has no left shift operation for vectors of 8 bit integers.
     constexpr uint32_t HIGH_ORDER_BITS_MASK = 0x80808080;
     Constant *ConstantMask = Ctx->getConstantInt32(HIGH_ORDER_BITS_MASK);
     Variable *Reg = makeReg(Ty, RegNum);
     _movd(Reg, legalize(ConstantMask, Legal_Reg | Legal_Mem));
     _pshufd(Reg, Reg, Ctx->getConstantZero(IceType_i8));
     return Reg;
   }
 }
 
 /// Construct a mask in a register that can be and'ed with a floating-point
 /// value to mask off its sign bit. The value will be <4 x 0x7fffffff> for f32
 /// and v4f32, and <2 x 0x7fffffffffffffff> for f64. Construct it as vector of
 /// ones logically right shifted one bit.
 // TODO(stichnot): Fix the wala
 // TODO: above, to represent vector constants in memory.
 template <typename TraitsType>
 Variable *TargetX86Base<TraitsType>::makeVectorOfFabsMask(Type Ty,
-                                                          int32_t RegNum) {
+                                                          RegNumT RegNum) {
   Variable *Reg = makeVectorOfMinusOnes(Ty, RegNum);
   _psrl(Reg, Ctx->getConstantInt8(1));
   return Reg;
 }
 
 template <typename TraitsType>
 typename TargetX86Base<TraitsType>::X86OperandMem *
 TargetX86Base<TraitsType>::getMemoryOperandForStackSlot(Type Ty, Variable *Slot,
                                                         uint32_t Offset) {
   // Ensure that Loc is a stack slot.
   assert(Slot->mustNotHaveReg());
-  assert(Slot->getRegNum() == Variable::NoRegister);
+  assert(Slot->getRegNum() == RegNumT::NoRegister);
   // Compute the location of Loc in memory.
   // TODO(wala,stichnot): lea should not
   // be required. The address of the stack slot is known at compile time
   // (although not until after addProlog()).
   constexpr Type PointerType = IceType_i32;
   Variable *Loc = makeReg(PointerType);
   _lea(Loc, Slot);
   Constant *ConstantOffset = Ctx->getConstantInt32(Offset);
   return X86OperandMem::create(Func, Ty, Loc, ConstantOffset);
 }
@@ skipping 20 matching lines @@
 ///
 /// Note #2.  ConstantRelocatable operands are also put through this process
 /// (not truncated directly) because our ELF emitter does R_386_32 relocations
 /// but not R_386_8 relocations.
 ///
 /// Note #3.  If Src is a Variable, the result will be an infinite-weight i8
 /// Variable with the RCX86_IsTrunc8Rcvr register class.  As such, this helper
 /// is a convenient way to prevent ah/bh/ch/dh from being an (invalid) argument
 /// to the pinsrb instruction.
 template <typename TraitsType>
-Variable *TargetX86Base<TraitsType>::copyToReg8(Operand *Src, int32_t RegNum) {
+Variable *TargetX86Base<TraitsType>::copyToReg8(Operand *Src, RegNumT RegNum) {
   Type Ty = Src->getType();
   assert(isScalarIntegerType(Ty));
   assert(Ty != IceType_i1);
   Variable *Reg = makeReg(IceType_i8, RegNum);
   Reg->setRegClass(RCX86_IsTrunc8Rcvr);
   if (llvm::isa<Variable>(Src) || llvm::isa<ConstantRelocatable>(Src)) {
     Variable *SrcTruncable = makeReg(Ty);
     switch (Ty) {
     case IceType_i64:
       SrcTruncable->setRegClass(RCX86_Is64To8);
@@ skipping 14 matching lines @@
     _mov(SrcRcvr, SrcTruncable);
     Src = SrcRcvr;
   }
   _mov(Reg, Src);
   return Reg;
 }
 
 /// Helper for legalize() to emit the right code to lower an operand to a
 /// register of the appropriate type.
 template <typename TraitsType>
-Variable *TargetX86Base<TraitsType>::copyToReg(Operand *Src, int32_t RegNum) {
+Variable *TargetX86Base<TraitsType>::copyToReg(Operand *Src, RegNumT RegNum) {
   Type Ty = Src->getType();
   Variable *Reg = makeReg(Ty, RegNum);
   if (isVectorType(Ty)) {
     _movp(Reg, Src);
   } else {
     _mov(Reg, Src);
   }
   return Reg;
 }
 
 template <typename TraitsType>
 Operand *TargetX86Base<TraitsType>::legalize(Operand *From, LegalMask Allowed,
-                                             int32_t RegNum) {
+                                             RegNumT RegNum) {
   const bool UseNonsfi = Func->getContext()->getFlags().getUseNonsfi();
   const Type Ty = From->getType();
   // Assert that a physical register is allowed. To date, all calls to
   // legalize() allow a physical register. If a physical register needs to be
   // explicitly disallowed, then new code will need to be written to force a
   // spill.
   assert(Allowed & Legal_Reg);
   // If we're asking for a specific physical register, make sure we're not
   // allowing any other operand kinds. (This could be future work, e.g. allow
   // the shl shift amount to be either an immediate or in ecx.)
-  assert(RegNum == Variable::NoRegister || Allowed == Legal_Reg);
+  assert(RegNum == RegNumT::NoRegister || Allowed == Legal_Reg);
 
   // Substitute with an available infinite-weight variable if possible.  Only do
   // this when we are not asking for a specific register, and when the
   // substitution is not locked to a specific register, and when the types
   // match, in order to capture the vast majority of opportunities and avoid
   // corner cases in the lowering.
-  if (RegNum == Variable::NoRegister) {
+  if (RegNum == RegNumT::NoRegister) {
     if (Variable *Subst = getContext().availabilityGet(From)) {
       // At this point we know there is a potential substitution available.
       if (Subst->mustHaveReg() && !Subst->hasReg()) {
         // At this point we know the substitution will have a register.
         if (From->getType() == Subst->getType()) {
           // At this point we know the substitution's register is compatible.
           return Subst;
         }
       }
     }
@@ skipping 40 matching lines @@
         return From;
       Const = llvm::cast<Constant>(From);
     }
     // There should be no constants of vector type (other than undef).
     assert(!isVectorType(Ty));
 
     // If the operand is a 64 bit constant integer we need to legalize it to a
     // register in x86-64.
     if (Traits::Is64Bit) {
       if (llvm::isa<ConstantInteger64>(Const)) {
-        if (RegNum != Variable::NoRegister) {
+        if (RegNum != RegNumT::NoRegister) {
           assert(Traits::getGprForType(IceType_i64, RegNum) == RegNum);
         }
         return copyToReg(Const, RegNum);
       }
     }
 
     // If the operand is an 32 bit constant integer, we should check whether we
     // need to randomize it or pool it.
     if (auto *C = llvm::dyn_cast<ConstantInteger32>(Const)) {
       Operand *NewConst = randomizeOrPoolImmediate(C, RegNum);
@@ skipping 62 matching lines @@
     if (MustRematerialize) {
       assert(Ty == IceType_i32);
       Variable *NewVar = makeReg(Ty, RegNum);
       // Since Var is rematerializable, the offset will be added when the lea is
       // emitted.
       constexpr Constant *NoOffset = nullptr;
       auto *Mem = X86OperandMem::create(Func, Ty, Var, NoOffset);
       _lea(NewVar, Mem);
       From = NewVar;
     } else if ((!(Allowed & Legal_Mem) && !MustHaveRegister) ||
-               (RegNum != Variable::NoRegister && RegNum != Var->getRegNum())) {
+               (RegNum != RegNumT::NoRegister && RegNum != Var->getRegNum())) {
       From = copyToReg(From, RegNum);
     }
     return From;
   }
 
   llvm::report_fatal_error("Unhandled operand kind in legalize()");
   return From;
 }
 
 /// Provide a trivial wrapper to legalize() for this common usage.
 template <typename TraitsType>
 Variable *TargetX86Base<TraitsType>::legalizeToReg(Operand *From,
-                                                   int32_t RegNum) {
+                                                   RegNumT RegNum) {
   return llvm::cast<Variable>(legalize(From, Legal_Reg, RegNum));
 }
 
 /// Legalize undef values to concrete values.
 template <typename TraitsType>
 Operand *TargetX86Base<TraitsType>::legalizeUndef(Operand *From,
-                                                  int32_t RegNum) {
+                                                  RegNumT RegNum) {
   Type Ty = From->getType();
   if (llvm::isa<ConstantUndef>(From)) {
     // Lower undefs to zero.  Another option is to lower undefs to an
     // uninitialized register; however, using an uninitialized register results
     // in less predictable code.
     //
     // If in the future the implementation is changed to lower undef values to
     // uninitialized registers, a FakeDef will be needed:
     //     Context.insert<InstFakeDef>(Reg);
     // This is in order to ensure that the live range of Reg is not
@@ skipping 58 matching lines @@
     // assert that PIC legalization has been applied.
     Mem = X86OperandMem::create(Func, Ty, Base, Offset);
   }
   // Do legalization, which contains randomization/pooling or do
   // randomization/pooling.
   return llvm::cast<X86OperandMem>(DoLegalize ? legalize(Mem)
                                               : randomizeOrPoolImmediate(Mem));
 }
 
 template <typename TraitsType>
-Variable *TargetX86Base<TraitsType>::makeReg(Type Type, int32_t RegNum) {
+Variable *TargetX86Base<TraitsType>::makeReg(Type Type, RegNumT RegNum) {
   // There aren't any 64-bit integer registers for x86-32.
   assert(Traits::Is64Bit || Type != IceType_i64);
   Variable *Reg = Func->makeVariable(Type);
-  if (RegNum == Variable::NoRegister)
+  if (RegNum == RegNumT::NoRegister)
     Reg->setMustHaveReg();
   else
     Reg->setRegNum(RegNum);
   return Reg;
 }
 
 template <typename TraitsType>
 const Type TargetX86Base<TraitsType>::TypeForSize[] = {
     IceType_i8, IceType_i16, IceType_i32, IceType_f64, IceType_v16i8};
 template <typename TraitsType>
@@ skipping 22 matching lines @@
 
 template <typename TraitsType> void TargetX86Base<TraitsType>::postLower() {
   if (Ctx->getFlags().getOptLevel() == Opt_m1)
     return;
   markRedefinitions();
   Context.availabilityUpdate();
 }
 
 template <typename TraitsType>
 void TargetX86Base<TraitsType>::makeRandomRegisterPermutation(
-    llvm::SmallVectorImpl<int32_t> &Permutation,
+    llvm::SmallVectorImpl<RegNumT> &Permutation,
     const llvm::SmallBitVector &ExcludeRegisters, uint64_t Salt) const {
   Traits::makeRandomRegisterPermutation(Ctx, Func, Permutation,
                                         ExcludeRegisters, Salt);
 }
 
 template <typename TraitsType>
 void TargetX86Base<TraitsType>::emit(const ConstantInteger32 *C) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Ctx->getStrEmit();
@@ skipping 40 matching lines @@
   assert(!Ctx->getFlags().getUseNonsfi() || C->getName() == GlobalOffsetTable);
   Ostream &Str = Ctx->getStrEmit();
   Str << "$";
   emitWithoutPrefix(C);
 }
 
 /// Randomize or pool an Immediate.
 template <typename TraitsType>
 Operand *
 TargetX86Base<TraitsType>::randomizeOrPoolImmediate(Constant *Immediate,
-                                                    int32_t RegNum) {
+                                                    RegNumT RegNum) {
   assert(llvm::isa<ConstantInteger32>(Immediate) ||
          llvm::isa<ConstantRelocatable>(Immediate));
   if (Ctx->getFlags().getRandomizeAndPoolImmediatesOption() == RPI_None ||
       RandomizationPoolingPaused == true) {
     // Immediates randomization/pooling off or paused
     return Immediate;
   }
 
   if (Traits::Is64Bit && NeedSandboxing) {
     // Immediate randomization/pooling is currently disabled for x86-64
@@ skipping 64 matching lines @@
         X86OperandMem::create(Func, Immediate->getType(), NoBase, Symbol);
     _mov(Reg, MemOperand);
     return Reg;
   }
   }
 }
 
 template <typename TraitsType>
 typename TargetX86Base<TraitsType>::X86OperandMem *
 TargetX86Base<TraitsType>::randomizeOrPoolImmediate(X86OperandMem *MemOperand,
-                                                    int32_t RegNum) {
+                                                    RegNumT RegNum) {
   assert(MemOperand);
   if (Ctx->getFlags().getRandomizeAndPoolImmediatesOption() == RPI_None ||
       RandomizationPoolingPaused == true) {
     // immediates randomization/pooling is turned off
     return MemOperand;
   }
 
   if (Traits::Is64Bit && NeedSandboxing) {
     // Immediate randomization/pooling is currently disabled for x86-64
     // sandboxing for it could generate invalid memory operands.
@@ skipping 64 matching lines @@
     // TO:
     //  insert: mov $label, RegTemp
     //  insert: lea [base, RegTemp], RegTemp
     //  =>[RegTemp, index, shift]
 
     // Memory operand should never exist as source operands in phi lowering
     // assignments, so there is no need to reuse any registers here. For
     // phi lowering, we should not ask for new physical registers in
     // general. However, if we do meet Memory Operand during phi lowering,
     // we should not blind or pool the immediates for now.
-    if (RegNum != Variable::NoRegister)
+    if (RegNum != RegNumT::NoRegister)
       return MemOperand;
     Variable *RegTemp = makeReg(IceType_i32);
     IceString Label;
     llvm::raw_string_ostream Label_stream(Label);
     MemOperand->getOffset()->emitPoolLabel(Label_stream, Ctx);
     MemOperand->getOffset()->setShouldBePooled(true);
     constexpr RelocOffsetT SymOffset = 0;
     constexpr bool SuppressMangling = true;
     Constant *Symbol =
         Ctx->getConstantSym(SymOffset, Label_stream.str(), SuppressMangling);
@@ skipping 164 matching lines @@
         emitGlobal(*Var, SectionSuffix);
       }
     }
   } break;
   }
 }
 } // end of namespace X86NAMESPACE
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H