Subzero: Use a proper RegNumT type instead of int32_t/SizeT.

src/IceTargetLoweringARM32.h

 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 60 matching lines @@
     Computations.forgetProducers();
     Computations.recordProducers(Node);
     Computations.dump(Func);
   }
 
   void translateOm1() override;
   void translateO2() override;
   bool doBranchOpt(Inst *I, const CfgNode *NextNode) override;
 
   SizeT getNumRegisters() const override { return RegARM32::Reg_NUM; }
-  Variable *getPhysicalRegister(SizeT RegNum, Type Ty = IceType_void) override;
-  IceString getRegName(SizeT RegNum, Type Ty) const override;
+  Variable *getPhysicalRegister(RegNumT RegNum,
+                                Type Ty = IceType_void) override;
+  IceString getRegName(RegNumT RegNum, Type Ty) const override;
   llvm::SmallBitVector getRegisterSet(RegSetMask Include,
                                       RegSetMask Exclude) const override;
   const llvm::SmallBitVector &
   getRegistersForVariable(const Variable *Var) const override {
     RegClass RC = Var->getRegClass();
     assert(RC < RC_Target);
     return TypeToRegisterSet[RC];
   }
   const llvm::SmallBitVector &
   getAllRegistersForVariable(const Variable *Var) const override {
     RegClass RC = Var->getRegClass();
     assert(RC < RC_Target);
     return TypeToRegisterSetUnfiltered[RC];
   }
-  const llvm::SmallBitVector &getAliasesForRegister(SizeT Reg) const override {
+  const llvm::SmallBitVector &
+  getAliasesForRegister(RegNumT Reg) const override {
     return RegisterAliases[Reg];
   }
   bool hasFramePointer() const override { return UsesFramePointer; }
   void setHasFramePointer() override { UsesFramePointer = true; }
-  SizeT getStackReg() const override { return RegARM32::Reg_sp; }
-  SizeT getFrameReg() const override { return RegARM32::Reg_fp; }
-  SizeT getFrameOrStackReg() const override {
+  RegNumT getStackReg() const override { return RegARM32::Reg_sp; }
+  RegNumT getFrameReg() const override { return RegARM32::Reg_fp; }
+  RegNumT getFrameOrStackReg() const override {
     return UsesFramePointer ? getFrameReg() : getStackReg();
   }
-  int32_t getReservedTmpReg() const { return RegARM32::Reg_ip; }
+  RegNumT getReservedTmpReg() const { return RegARM32::Reg_ip; }
 
   size_t typeWidthInBytesOnStack(Type Ty) const override {
     // Round up to the next multiple of 4 bytes. In particular, i1, i8, and i16
     // are rounded up to 4 bytes.
     return (typeWidthInBytes(Ty) + 3) & ~3;
   }
   uint32_t getStackAlignment() const override;
   void reserveFixedAllocaArea(size_t Size, size_t Align) override {
     FixedAllocaSizeBytes = Size;
     assert(llvm::isPowerOf2_32(Align));
@@ skipping 39 matching lines @@
   enum OperandLegalization {
     Legal_Reg = 1 << 0,  /// physical register, not stack location
     Legal_Flex = 1 << 1, /// A flexible operand2, which can hold rotated small
                          /// immediates, shifted registers, or modified fp imm.
     Legal_Mem = 1 << 2,  /// includes [r0, r1 lsl #2] as well as [sp, #12]
     Legal_Rematerializable = 1 << 3,
     Legal_Default = ~Legal_Rematerializable,
   };
 
   using LegalMask = uint32_t;
-  Operand *legalizeUndef(Operand *From, int32_t RegNum = Variable::NoRegister);
+  Operand *legalizeUndef(Operand *From, RegNumT RegNum = RegNumT::NoRegister);
   Operand *legalize(Operand *From, LegalMask Allowed = Legal_Default,
-                    int32_t RegNum = Variable::NoRegister);
-  Variable *legalizeToReg(Operand *From, int32_t RegNum = Variable::NoRegister);
+                    RegNumT RegNum = RegNumT::NoRegister);
+  Variable *legalizeToReg(Operand *From, RegNumT RegNum = RegNumT::NoRegister);
 
   OperandARM32ShAmtImm *shAmtImm(uint32_t ShAmtImm) const {
     assert(ShAmtImm < 32);
     return OperandARM32ShAmtImm::create(
         Func,
         llvm::cast<ConstantInteger32>(Ctx->getConstantInt32(ShAmtImm & 0x1F)));
   }
 
   GlobalContext *getCtx() const { return Ctx; }
 
@@ skipping 72 matching lines @@
   uint32_t getCallStackArgumentsSizeBytes(const InstCall *Instr) override;
   void genTargetHelperCallFor(Inst *Instr) override;
   void doAddressOptLoad() override;
   void doAddressOptStore() override;
   void randomlyInsertNop(float Probability,
                          RandomNumberGenerator &RNG) override;
 
   OperandARM32Mem *formMemoryOperand(Operand *Ptr, Type Ty);
 
   Variable64On32 *makeI64RegPair();
-  Variable *makeReg(Type Ty, int32_t RegNum = Variable::NoRegister);
+  Variable *makeReg(Type Ty, RegNumT RegNum = RegNumT::NoRegister);
   static Type stackSlotType();
-  Variable *copyToReg(Operand *Src, int32_t RegNum = Variable::NoRegister);
+  Variable *copyToReg(Operand *Src, RegNumT RegNum = RegNumT::NoRegister);
   void alignRegisterPow2(Variable *Reg, uint32_t Align,
-                         int32_t TmpRegNum = Variable::NoRegister);
+                         RegNumT TmpRegNum = RegNumT::NoRegister);
 
   /// Returns a vector in a register with the given constant entries.
-  Variable *makeVectorOfZeros(Type Ty, int32_t RegNum = Variable::NoRegister);
+  Variable *makeVectorOfZeros(Type Ty, RegNumT RegNum = RegNumT::NoRegister);
 
   void
-  makeRandomRegisterPermutation(llvm::SmallVectorImpl<int32_t> &Permutation,
+  makeRandomRegisterPermutation(llvm::SmallVectorImpl<RegNumT> &Permutation,
                                 const llvm::SmallBitVector &ExcludeRegisters,
                                 uint64_t Salt) const override;
 
   // If a divide-by-zero check is needed, inserts a: test; branch .LSKIP; trap;
   // .LSKIP: <continuation>. If no check is needed nothing is inserted.
   void div0Check(Type Ty, Operand *SrcLo, Operand *SrcHi);
   using ExtInstr = void (TargetARM32::*)(Variable *, Variable *,
                                          CondARM32::Cond);
   using DivInstr = void (TargetARM32::*)(Variable *, Variable *, Variable *,
                                          CondARM32::Cond);
@@ skipping 702 matching lines @@
     /// Legalizes Mov if its Source (or Destination) is a spilled Variable, or
     /// if its Source is a Rematerializable variable (this form is used in lieu
     /// of lea, which is not available in ARM.)
     ///
     /// Moves to memory become store instructions, and moves from memory, loads.
     void legalizeMov(InstARM32Mov *Mov);
 
   private:
     /// Creates a new Base register centered around [Base, +/- Offset].
     Variable *newBaseRegister(Variable *Base, int32_t Offset,
-                              int32_t ScratchRegNum);
+                              RegNumT ScratchRegNum);
 
     /// Creates a new, legal OperandARM32Mem for accessing Base + Offset.
     /// The returned mem operand is a legal operand for accessing memory that is
     /// of type Ty.
     ///
     /// If [Base, #Offset] is encodable, then the method returns a Mem operand
     /// expressing it. Otherwise,
     ///
     /// if [TempBaseReg, #Offset-TempBaseOffset] is a valid memory operand, the
     /// method will return that. Otherwise,
@@ skipping 46 matching lines @@
     CallingConv &operator=(const CallingConv &) = delete;
 
   public:
     CallingConv();
     ~CallingConv() = default;
 
     /// argInGPR returns true if there is a GPR available for the requested
     /// type, and false otherwise. If it returns true, Reg is set to the
     /// appropriate register number. Note that, when Ty == IceType_i64, Reg will
     /// be an I64 register pair.
-    bool argInGPR(Type Ty, int32_t *Reg);
+    bool argInGPR(Type Ty, RegNumT *Reg);
 
     /// argInVFP is to floating-point/vector types what argInGPR is for integer
     /// types.
-    bool argInVFP(Type Ty, int32_t *Reg);
+    bool argInVFP(Type Ty, RegNumT *Reg);
 
   private:
-    void discardUnavailableGPRsAndTheirAliases(CfgVector<SizeT> *Regs);
+    void discardUnavailableGPRsAndTheirAliases(CfgVector<RegNumT> *Regs);
     llvm::SmallBitVector GPRegsUsed;
-    CfgVector<SizeT> GPRArgs;
-    CfgVector<SizeT> I64Args;
+    CfgVector<RegNumT> GPRArgs;
+    CfgVector<RegNumT> I64Args;
 
-    void discardUnavailableVFPRegs(CfgVector<SizeT> *Regs);
+    void discardUnavailableVFPRegs(CfgVector<RegNumT> *Regs);
     llvm::SmallBitVector VFPRegsUsed;
-    CfgVector<SizeT> FP32Args;
-    CfgVector<SizeT> FP64Args;
-    CfgVector<SizeT> Vec128Args;
+    CfgVector<RegNumT> FP32Args;
+    CfgVector<RegNumT> FP64Args;
+    CfgVector<RegNumT> Vec128Args;
   };
 
 private:
   ENABLE_MAKE_UNIQUE;
 
   OperandARM32Mem *formAddressingMode(Type Ty, Cfg *Func, const Inst *LdSt,
                                       Operand *Base);
 
   void postambleCtpop64(const InstCall *Instr);
   void preambleDivRem(const InstCall *Instr);
@@ skipping 127 matching lines @@
 private:
   ~TargetHeaderARM32() = default;
 
   TargetARM32Features CPUFeatures;
 };
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H