Subzero: Use a proper RegNumT type instead of int32_t/SizeT.

src/IceTargetLowering.cpp

 //===- subzero/src/IceTargetLowering.cpp - Basic lowering implementation --===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 101 matching lines @@
 Variable *LoweringContext::availabilityGet(Operand *Src) const {
   assert(Src);
   if (Src == LastDest)
     return LastSrc;
   return nullptr;
 }
 
 namespace {
 
 void printRegisterSet(Ostream &Str, const llvm::SmallBitVector &Bitset,
-                      std::function<IceString(int32_t)> getRegName,
+                      std::function<IceString(RegNumT)> getRegName,
                       const IceString &LineIndentString) {
   constexpr size_t RegistersPerLine = 16;
   size_t Count = 0;
-  for (int i = Bitset.find_first(); i != -1; i = Bitset.find_next(i)) {
+  for (RegNumT RegNum : RegNumBitVector(Bitset)) {
     if (Count == 0) {
       Str << LineIndentString;
     } else {
       Str << ",";
     }
     if (Count > 0 && Count % RegistersPerLine == 0)
       Str << "\n" << LineIndentString;
     ++Count;
-    Str << getRegName(i);
+    Str << getRegName(RegNum);
   }
   if (Count)
     Str << "\n";
 }
 
 // Splits "<class>:<reg>" into "<class>" plus "<reg>".  If there is no <class>
 // component, the result is "" plus "<reg>".
 void splitToClassAndName(const IceString &RegName, IceString *SplitRegClass,
                          IceString *SplitRegName) {
   constexpr const char Separator[] = ":";
   constexpr size_t SeparatorWidth = llvm::array_lengthof(Separator) - 1;
   size_t Pos = RegName.find(Separator);
   if (Pos == std::string::npos) {
     *SplitRegClass = "";
     *SplitRegName = RegName;
   } else {
     *SplitRegClass = RegName.substr(0, Pos);
     *SplitRegName = RegName.substr(Pos + SeparatorWidth);
   }
 }
 
 } // end of anonymous namespace
 
 void TargetLowering::filterTypeToRegisterSet(
     GlobalContext *Ctx, int32_t NumRegs,
     llvm::SmallBitVector TypeToRegisterSet[], size_t TypeToRegisterSetSize,
-    std::function<IceString(int32_t)> getRegName,
+    std::function<IceString(RegNumT)> getRegName,
     std::function<IceString(RegClass)> getRegClassName) {
   std::vector<llvm::SmallBitVector> UseSet(TypeToRegisterSetSize,
                                            llvm::SmallBitVector(NumRegs));
   std::vector<llvm::SmallBitVector> ExcludeSet(TypeToRegisterSetSize,
                                                llvm::SmallBitVector(NumRegs));
 
-  std::unordered_map<IceString, int32_t> RegNameToIndex;
-  for (int32_t RegIndex = 0; RegIndex < NumRegs; ++RegIndex)
-    RegNameToIndex[getRegName(RegIndex)] = RegIndex;
+  std::unordered_map<IceString, RegNumT> RegNameToIndex;
+  for (int32_t RegIndex = 0; RegIndex < NumRegs; ++RegIndex) {
+    auto RegNum = RegNumT::fromInt(RegIndex);
+    RegNameToIndex[getRegName(RegNum)] = RegNum;
+  }
 
   ClFlags::StringVector BadRegNames;
 
   // The processRegList function iterates across the RegNames vector.  Each
   // entry in the vector is a string of the form "<reg>" or "<class>:<reg>".
   // The register class and register number are computed, and the corresponding
   // bit is set in RegSet[][].  If "<class>:" is missing, then the bit is set
   // for all classes.
   auto processRegList = [&](const ClFlags::StringVector &RegNames,
                             std::vector<llvm::SmallBitVector> &RegSet) {
@@ skipping 681 matching lines @@
   case Target_##X:                                                             \
     return ::X::createTargetHeaderLowering(Ctx);
 #include "llvm/Config/SZTargets.def"
 #undef SUBZERO_TARGET
   }
 }
 
 TargetHeaderLowering::~TargetHeaderLowering() = default;
 
 } // end of namespace Ice