Subzero: Use a proper RegNumT type instead of int32_t/SizeT.

src/IceInstARM32.cpp

 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 870 matching lines @@
 }
 
 void InstARM32RegisterStackOp::emitSRegsAsText(const Cfg *Func,
                                                const Variable *BaseReg,
                                                SizeT RegCount) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   Str << "\t" << getSRegOpcode() << "\t{";
   bool IsFirst = true;
-  int32_t Base = BaseReg->getRegNum();
+  auto Base = BaseReg->getRegNum();
   for (SizeT i = 0; i < RegCount; ++i) {
     if (IsFirst)
       IsFirst = false;
     else
       Str << ", ";
-    Str << RegARM32::getRegName(Base + i);
+    Str << RegARM32::getRegName(RegNumT::fixme(Base + i));
   }
   Str << "}";
 }
 
 namespace {
 
 bool isAssignedConsecutiveRegisters(const Variable *Before,
                                     const Variable *After) {
   assert(Before->hasReg());
   assert(After->hasReg());
-  return Before->getRegNum() + 1 == After->getRegNum();
+  return RegNumT::fixme(Before->getRegNum() + 1) == After->getRegNum();
 }
 
 } // end of anonymous namespace
 
 void InstARM32RegisterStackOp::emitUsingForm(const Cfg *Func,
                                              const EmitForm Form) const {
   SizeT NumRegs = getNumStackRegs();
   assert(NumRegs);
 
   const auto *Reg = llvm::cast<Variable>(getStackReg(0));
   if (isScalarIntegerType(Reg->getType())) {
     // Pop GPR registers.
     SizeT IntegerCount = 0;
     ARM32::IValueT GPRegisters = 0;
     const Variable *LastDest = nullptr;
     for (SizeT i = 0; i < NumRegs; ++i) {
       const Variable *Var = getStackReg(i);
       assert(Var->hasReg() && "stack op only applies to registers");
-      int32_t Reg = RegARM32::getEncodedGPR(Var->getRegNum());
+      RegARM32::GPRRegister Reg = RegARM32::getEncodedGPR(Var->getRegNum());
       LastDest = Var;
       GPRegisters |= (1 << Reg);
       ++IntegerCount;
     }
     if (IntegerCount == 1) {
       emitSingleGPR(Func, Form, LastDest);
     } else {
       emitMultipleGPRs(Func, Form, GPRegisters);
     }
   } else {
@@ skipping 1603 matching lines @@
 
 template class InstARM32FourAddrGPR<InstARM32::Mla>;
 template class InstARM32FourAddrGPR<InstARM32::Mls>;
 
 template class InstARM32CmpLike<InstARM32::Cmn>;
 template class InstARM32CmpLike<InstARM32::Cmp>;
 template class InstARM32CmpLike<InstARM32::Tst>;
 
 } // end of namespace ARM32
 } // end of namespace Ice